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commit 47042a60140be61ba1fc00a28099b35356c6f35e Author: raiden00pl <[email protected]> AuthorDate: Mon Sep 14 12:54:11 2026 +0200 arch/arm/stm32c0: Fix RCC CRS and HSIUSB48 bits APB1 bit 16 is CRS, not CRC (CRC is on AHB). RCC_CRRCR only holds the HSIUSB48 calibration; the HSIUSB48 enable lives in RCC_CR. Assisted-by: Claude Code Signed-off-by: raiden00pl <[email protected]> --- arch/arm/src/stm32c0/hardware/stm32c0_rcc.h | 14 +++++--------- arch/arm/src/stm32c0/stm32c0_rcc.c | 6 ------ 2 files changed, 5 insertions(+), 15 deletions(-) diff --git a/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h b/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h index 9784111a9b1..2ead7025a00 100644 --- a/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h @@ -142,13 +142,9 @@ /* Clock recovery RC register */ -#define RCC_CRRCR_HSI48ON (1 << 0) /* Bits 0: 48MHz HSI clock enable */ -#define RCC_CRRCR_HSI48RDY (1 << 1) /* Bits 1: 48MHz HSI clock ready */ -#define RCC_CRRCR_HSI48DIV6EN (1 << 2) /* Bits 2: 48MHz HSI clock divided by 6 output enable */ - /* Bits 3-7: Reserved */ -#define RCC_CRRCR_HSI48CAL_SHIFT (8) /* Bits 8: 48 MHz HSI reset calibration */ -#define RCC_CRRCR_HSI48CAL_MASK (0xff << RCC_CRRCR_HSI48CAL_SHIFT) - /* Bits 16-31: Reserved */ +#define RCC_CRRCR_HSIUSB48CAL_SHIFT (0) /* Bits 0-8: HSIUSB48 clock calibration */ +#define RCC_CRRCR_HSIUSB48CAL_MASK (0x1ff << RCC_CRRCR_HSIUSB48CAL_SHIFT) + /* Bits 9-31: Reserved */ /* Clock configuration register */ @@ -240,7 +236,7 @@ #define RCC_APB1RSTR_USBRST (1 << 13) /* Bit 13: USB reset */ #define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */ /* Bit 15: Reserved */ -#define RCC_APB1RSTR_CRCRST (1 << 16) /* Bit 15: CRC reset */ +#define RCC_APB1RSTR_CRSRST (1 << 16) /* Bit 16: CRS reset */ #define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */ #define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */ #define RCC_APB1RSTR_USART4RST (1 << 19) /* Bit 19: USART 4 reset */ @@ -293,7 +289,7 @@ #define RCC_APB1ENR_USBEN (1 << 13) /* Bit 13: USB clock enable */ #define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 clock enable */ /* Bit 15: Reserved */ -#define RCC_APB1ENR_CRCEN (1 << 16) /* Bit 16: CRC clock enable */ +#define RCC_APB1ENR_CRSEN (1 << 16) /* Bit 16: CRS clock enable */ #define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */ #define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */ #define RCC_APB1ENR_USART4EN (1 << 19) /* Bit 19: USART 4 clock enable */ diff --git a/arch/arm/src/stm32c0/stm32c0_rcc.c b/arch/arm/src/stm32c0/stm32c0_rcc.c index ffa41fc0c6d..c46c41befdf 100644 --- a/arch/arm/src/stm32c0/stm32c0_rcc.c +++ b/arch/arm/src/stm32c0/stm32c0_rcc.c @@ -195,12 +195,6 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_USBEN; #endif -#ifdef CONFIG_STM32_CRC - /* CRC clock enable */ - - regval |= RCC_APB1ENR_CRCEN; -#endif - #ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */
