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commit 2b48c897b66ee4376669f151b13fdb4378960e85 Author: raiden00pl <[email protected]> AuthorDate: Tue Nov 3 09:57:28 2026 +0100 boards/nucleo-f746zg: Define the LPTIM1 kernel clock. LPTIM1 runs on PCLK1, selected by STM32_RCC_DCKCFGR2_LPTIM1SRC. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: raiden00pl <[email protected]> --- boards/arm/stm32f7/nucleo-f746zg/include/board.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/boards/arm/stm32f7/nucleo-f746zg/include/board.h b/boards/arm/stm32f7/nucleo-f746zg/include/board.h index 76615e8a384..b4d628bd530 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/include/board.h +++ b/boards/arm/stm32f7/nucleo-f746zg/include/board.h @@ -193,6 +193,10 @@ #define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +/* LPTIM1 kernel clock is PCLK1 (STM32_RCC_DCKCFGR2_LPTIM1SRC) */ + +#define STM32_LPTIM1_CLKIN STM32_PCLK1_FREQUENCY + /* SDMMC dividers. Note that slower clocking is required when DMA * is disabledin order to avoid RX overrun/TX underrun errors due * to delayed responses to service FIFOs in interrupt driven mode.
