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commit 524a0e11906402bb91087dd48be010dc26fcdd9f Author: raiden00pl <[email protected]> AuthorDate: Tue Nov 3 09:57:29 2026 +0100 boards/nucleo-u3c5zi-q: Define the LPTIM kernel clocks. LPTIM2 runs on PCLK1 and LPTIM1/3/4 on MSIK, the reset values of the RCC_CCIPR1 and RCC_CCIPR3 LPTIM source selections. MSIK is MSIRC1 / 2 (12 MHz), the RCC_ICSCR1 MSIKSEL and MSIKDIV reset values. Assisted-by: Claude Code:claude-opus-5-5 Signed-off-by: raiden00pl <[email protected]> --- boards/arm/stm32u3/nucleo-u3c5zi-q/include/board.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/boards/arm/stm32u3/nucleo-u3c5zi-q/include/board.h b/boards/arm/stm32u3/nucleo-u3c5zi-q/include/board.h index e8e99505305..70e57c5291a 100644 --- a/boards/arm/stm32u3/nucleo-u3c5zi-q/include/board.h +++ b/boards/arm/stm32u3/nucleo-u3c5zi-q/include/board.h @@ -93,6 +93,16 @@ #define STM32_TIM16_CLKIN STM32_PCLK2_FREQUENCY #define STM32_TIM17_CLKIN STM32_PCLK2_FREQUENCY +/* LPTIM kernel clocks (RCC_CCIPR1 LPTIM2SEL and RCC_CCIPR3 LPTIM1SEL / + * LPTIM34SEL reset values): LPTIM2 on PCLK1, LPTIM1/3/4 on MSIK + * (MSIRC1 24 MHz / 2, RCC_ICSCR1 MSIKSEL / MSIKDIV reset values) + */ + +#define STM32_LPTIM1_CLKIN 12000000ul +#define STM32_LPTIM2_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_LPTIM3_CLKIN 12000000ul +#define STM32_LPTIM4_CLKIN 12000000ul + /* USART1 is connected to the ST-LINK virtual COM port. */ #define GPIO_USART1_RX GPIO_USART1_RX_1
