xiaoxiang781216 commented on issue #8288: URL: https://github.com/apache/nuttx/issues/8288#issuecomment-1407340538
> http://www.st.com/resource/en/application_note/DM00272913.pdf > > <img alt="image" width="791" src="https://user-images.githubusercontent.com/25843920/215254927-3e46e886-d369-4b1c-b82e-bd2bb3aa7e08.png";> Is this ST specific extension? DMA normally need do the cache clean/invalidate explicitly. Only very complex/smart DMA master(e.g. GPU) which implement AXI ACE extension can participate with CPU cache coherency system: https://developer.arm.com/documentation/ihi0022/e/ACE-Protocol-Specification/About-ACE/Coherency-overview?lang=en I don't believe that Cortex-M IP will implement ACE. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
![https://user-images.githubusercontent.com/25843920/215254927-3e46e886-d369-4b1c-b82e-bd2bb3aa7e08.png"](https://user-images.githubusercontent.com/25843920/215254927-3e46e886-d369-4b1c-b82e-bd2bb3aa7e08.png"){kind=link}