davids5 commented on issue #8288: URL: https://github.com/apache/nuttx/issues/8288#issuecomment-1407581867
For the ARM Cortex-M7 > So I think to make the normal memory region cacheable, the shareable bit in MPU should be 0. In this case, cache coherency between CPU and DMA must be ensured by software. (i.e. clean/invalidate) I believe this to be correct and that `mpu_user_intsram` is incorrect. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
