masayuki2009 commented on issue #8288: URL: https://github.com/apache/nuttx/issues/8288#issuecomment-1407388293
@xiaoxiang781216 I think it's not ST-specific but ARM Cortex-M7-specific. In fact, in the application note for i.mxrt, as you can also seen in https://www.nxp.com/docs/en/application-note/AN12042.pdf It says that `Cache policy is fixed to Non-cacheable when Shareable bit is set, no matter what’s the TEX/C/B value. A full cache policy settings table can be found in ARM Cortex-M7 Processor User Guide` <img width="868" alt="image" src="https://user-images.githubusercontent.com/25843920/215265552-80957a6c-2a28-47cc-9fcd-96ce4d9e97b3.png";> So I think to make the normal memory region cacheable, the shareable bit in MPU should be 0. In this case, cache coherency between CPU and DMA must be ensured by software. (i.e. clean/invalidate) -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
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