pussuw commented on PR #9103: URL: https://github.com/apache/nuttx/pull/9103#issuecomment-1535984368
> > Now I think I understand what might be going on, and indeed the problem is that we save and restore the registers even if a context switch does not happen. > > I now remember what has happened, we needed to do this change #5905 because restoring the next task's FPU registers from the stack did not work with CONFIG_ARCH_ADDRENV=y because the wrong address environment was in use (stack virtual address points to wrong context). > > My suggestion is that we try again to do the lazy FPU save / restore only when a context switch happens, not when an exception is taken. What do you think @xiaoxiang781216 @SunJun8 ? > > @pussuw My patch aims to address the following issue: after completing exception handling when the FS bit in mstatus is not dirty, the fpu registers are still restored, leading to incorrect fpu register values. My patch does not change the timing of saving and restoring fpu registers, but ensures that fpu registers are only restored when the FS bit is dirty. @SunJun8 Yes I understand and it fixes loading the wrong registers. But IMHO the problem is that we use the lazy FPU feature incorrectly. It is fine by me to merge this patch, it looks good to me. But it fixes a problem we should not have in the first place. We have to keep in mind that the current lazy FPU implementation in RISC-V does extra work. FPU needs save/restore ONLY when the context changes. Maybe I can make an issue for it ? -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
