xiaoxiang781216 commented on code in PR #9103: URL: https://github.com/apache/nuttx/pull/9103#discussion_r1186793321
########## arch/risc-v/src/common/riscv_macros.S: ########## @@ -227,8 +222,15 @@ REGLOAD t0, REG_INT_CTX(\out) li t1, MSTATUS_FS and t2, t0, t1 - li t1, MSTATUS_FS_INIT - ble t2, t1, 1f + li t1, MSTATUS_FS_DIRTY + bne t2, t1, 1f + + /* Reset FS bit to MSTATUS_FS_CLEAN */ + li t1, MSTATUS_FS_CLEAN Review Comment: The implementation isn't optimized as arm version, you can see: https://github.com/apache/nuttx/blob/master/arch/arm/src/armv7-m/arm_exception.S#L181C18-L182 arm version doesn't reserve the space for FPU in this case. @no1wudi could you apply the same optimization to riscv? -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
