cbalint13 commented on code in PR #13621:
URL: https://github.com/apache/tvm/pull/13621#discussion_r1057926988
##########
python/tvm/relay/op/strategy/x86.py:
##########
@@ -627,16 +627,16 @@ def batch_matmul_strategy_cpu(attrs, inputs, out_type,
target):
if (
not attrs.transpose_a
and attrs.transpose_b
- and target_has_vnni(mcpu)
+ and target_has_avx512(mcpu)
and inputs[0].dtype == "uint8"
and inputs[1].dtype == "int8"
and inputs[1].shape[-2] % 16 == 0
and inputs[1].shape[-1] % 4 == 0
):
strategy.add_implementation(
- wrap_compute_batch_matmul(topi.x86.batch_matmul_vnni_compute,
need_out_dtype=True),
- wrap_topi_schedule(topi.x86.schedule_batch_matmul_vnni),
- name="batch_matmul_vnni.x86",
Review Comment:
> The instruction set for SSE/AVX2/AVX512 for int8 is absolutely the same,
the only difference is the number of lanes.
Yes, same class doing integer dot products on immediate registers, but
mention:
- *different* clocking, timing & implementation on ASIC
- (auto)tensorization opportunities differ as inner loops match
*differently*
> Additionally, the patterns how these int8 instructions
(VPMADDUBSW/VPMADDWD/VPADDD) are used, is the >same as the only VNNI
instruction (VPDPBUSD).
Right.
- VNNI insn. accumulates into int32 lanes in single step: vpdpbusd
- AVX512 (incl. AVX2, SSSE3 ones) does same in two-step, e.g: pmaddubs +
pmadd
> I.e. it is reasonable to have the only tvm intrinsic, it is reasonable to
remove VNNI from the name of the function, and it is reasonable to extend these
intrinsic function to SSE and AVX2 that is not done yet in this PR
- Indeed the proposed intrinsic merger is perfectly fine.
- It was possible to question it with reasonable arguments.
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