cbalint13 commented on code in PR #13621:
URL: https://github.com/apache/tvm/pull/13621#discussion_r1057955355
##########
python/tvm/relay/op/strategy/x86.py:
##########
@@ -627,16 +627,16 @@ def batch_matmul_strategy_cpu(attrs, inputs, out_type,
target):
if (
not attrs.transpose_a
and attrs.transpose_b
- and target_has_vnni(mcpu)
+ and target_has_avx512(mcpu)
and inputs[0].dtype == "uint8"
and inputs[1].dtype == "int8"
and inputs[1].shape[-2] % 16 == 0
and inputs[1].shape[-1] % 4 == 0
):
strategy.add_implementation(
- wrap_compute_batch_matmul(topi.x86.batch_matmul_vnni_compute,
need_out_dtype=True),
- wrap_topi_schedule(topi.x86.schedule_batch_matmul_vnni),
- name="batch_matmul_vnni.x86",
Review Comment:
> > different clocking, timing & implementation on ASIC
>
> What kind of ASIC do you mean?
* CPU, family of x86, different generations, varying extended ISA layouts:
amx avx512 vnni avx2 ssse3 sse2
> > (auto)tensorization opportunities differ as inner loops match differently
> Under `tensorization opportunities differ` do yo mean different number of
lanes for different instruction set which can be reflected in potential
different blocking size?
* Yes, both input-widths and output-lanes yields different outcomes, varying
performances.
* E.g. autotensorizer will opportunistically search to permute & match inner
loops to these varying sizes.
> Or something else?
* TVM is a compiler after all, to my knowledge the only one capable of
auto-tensorization with arbitrary intrinsic.
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