cbalint13 commented on code in PR #13621:
URL: https://github.com/apache/tvm/pull/13621#discussion_r1057198498
##########
python/tvm/relay/op/strategy/x86.py:
##########
@@ -627,16 +627,16 @@ def batch_matmul_strategy_cpu(attrs, inputs, out_type,
target):
if (
not attrs.transpose_a
and attrs.transpose_b
- and target_has_vnni(mcpu)
+ and target_has_avx512(mcpu)
and inputs[0].dtype == "uint8"
and inputs[1].dtype == "int8"
and inputs[1].shape[-2] % 16 == 0
and inputs[1].shape[-1] % 4 == 0
):
strategy.add_implementation(
- wrap_compute_batch_matmul(topi.x86.batch_matmul_vnni_compute,
need_out_dtype=True),
- wrap_topi_schedule(topi.x86.schedule_batch_matmul_vnni),
- name="batch_matmul_vnni.x86",
Review Comment:
> know VNNI is a part of AVX512 architectures. The fork is here:
>https://github.com/apache/tvm/blob/main/python/tvm/topi/x86/tensor_intrin.py#:~:text=def%20dot_16x1x16_uint8_int8_int32()%3A,return%20dot_16x1x16_uint8_int8_int32_skylake()
> As you correctly remarked avx2 and ssse3 are also processed here, but they
are not accessable due to high-level check target_has_avx512.
Can't see original **llvm.x86.vnni** instrinsic one in the above.
This switch, right in the provided **tensor_intrin.py** fork:
```
if target_has_vnni(mcpu):
# VNNI capable platform
return dot_16x1x16_uint8_int8_int32_cascadelake()
# vpmaddubsw/vpmaddwd fallback
return dot_16x1x16_uint8_int8_int32_skylake()
```
As +SIMD keeps coming, would't be better to stay as upcoming
[strategy/x86.py](https://github.com/apache/tvm/blob/dd1eb2498a4e2c867a16d7d9ccea010c396e10ae/python/tvm/relay/op/strategy/x86.py#L594-L621)
```if/elif``` + preferential ```plevel``` ?
* The **tensor_intrin.py** would remain only a enumeration of SIMD (no
decisions), triages would stay **strategy**, etc.
* User may control the fall into right strategy by narrowing ```"llvm
+mattr={avx512bw,avxvnni,...}"```, as [llvm
flags](https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Basic/BuiltinsX86.def).
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