cbalint13 commented on code in PR #13621:
URL: https://github.com/apache/tvm/pull/13621#discussion_r1057322567
##########
python/tvm/relay/op/strategy/x86.py:
##########
@@ -627,16 +627,16 @@ def batch_matmul_strategy_cpu(attrs, inputs, out_type,
target):
if (
not attrs.transpose_a
and attrs.transpose_b
- and target_has_vnni(mcpu)
+ and target_has_avx512(mcpu)
and inputs[0].dtype == "uint8"
and inputs[1].dtype == "int8"
and inputs[1].shape[-2] % 16 == 0
and inputs[1].shape[-1] % 4 == 0
):
strategy.add_implementation(
- wrap_compute_batch_matmul(topi.x86.batch_matmul_vnni_compute,
need_out_dtype=True),
- wrap_topi_schedule(topi.x86.schedule_batch_matmul_vnni),
- name="batch_matmul_vnni.x86",
Review Comment:
> Hello @cbalint13! Your view looks reasonable and there is no problems to
reimplement it from my side. But I did not implement method
`dot_16x1x16_uint8_int8_int32` with conditions on tensor_intrin.py side and
thought that it is brick to build some concept. @elvin-n and @jwfromm what do
you think about Balint's view?
@vvchernov ,
Thanks for clarifications, I see your point, it is perfectly fine way too.
I think by making all CI tests to pass in green more reviewers will come.
---
I try sum up, on this very pinned PR change on **strategy/x86.py**, visibile
on top of this thread:
```
-from tvm.topi.x86.utils import target_has_vnni
+from tvm.topi.x86.utils import target_has_avx512
- and target_has_vnni(mcpu)
+ and target_has_avx512(mcpu)
- wrap_compute_dense(topi.x86.dense_vnni),
- wrap_topi_schedule(topi.x86.schedule_dense_vnni),
+ wrap_compute_dense(topi.x86.dense_int8),
+ wrap_topi_schedule(topi.x86.schedule_dense_int8),
```
* This merge vnni to avx512 (under new **dense_int8** umbrella) arguing that
VNNI is subset of AVX512 group.
* VNNI is subset of AVX512 group, however there are CPU having AVX512 but
**no VNNI** [1].
[1] https://en.wikipedia.org/wiki/AVX-512#VNNI
My view was to leave separate avx512 & vnni(as was) in strategy/x86.py (not
to merge vnni->avx512)
My argument was to triage any SIMD right in **strategy/x86.py** as upcoming
AMX do
[here](https://github.com/apache/tvm/blob/dd1eb2498a4e2c867a16d7d9ccea010c396e10ae/python/tvm/relay/op/strategy/x86.py#L594-L621)
+ plevel control.
I saw VNNI and AVX512 +(AVX2, SSSE3) as potentialy independend things,
moreover choosable via "llvm +mattr=...".
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