On Wed, 12 Mar 2003 10:58:08 -0800 (PST), Todd Lyons wrote: > > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > Teemu Torma wrote on Wed, Mar 12, 2003 at 01:36:50PM +0100 : > > > > Processor #0 Pentium 4(tm) XEON(tm) APIC version 16 > > ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled) > > Processor #2 Pentium 4(tm) XEON(tm) APIC version 16 > > ACPI: LAPIC (acpi_id[0x03] lapic_id[0x01] disabled) > > ACPI: LAPIC (acpi_id[0x04] lapic_id[0x03] disabled) > > ACPI: IOAPIC (id[0x02] address[0xfec00000] global_irq_base[0x0]) > > It's doing it here too. It's calling it CPU0 and CPU2 instead of CPU0 > and CPU1. > > Blue skies... Todd > - -- > MandrakeSoft USA <a href="http://www.mandrakesoft.com";>http://www.mandrakesoft.com</a> > cat /boot/vmlinuz > /dev/dsp #for great justice > Mandrake Cooker Devel Version, Kernel 2.4.21-0.13mdk > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.2.1 (GNU/Linux) > > iD8DBQE+b33hlp7v05cW2woRArgOAJ9y+slOKxinYfqWRNpMH8HLtAtrHwCgkMIs > D/j/ZfXIq5/g5Ml0G8Z7PEY= > =IjhA > -----END PGP SIGNATURE----- Just curious, since I don't know if the code is in the 2.4 kernel, but are those processors new enough to have hyperthreading capability? Then it would be assigning the interrupts by hardware CPU, not by logical CPU. CPU0 and CPU1 would be the first physical CPU, CPU2 and CPU3 would be the second physical CPU.
Paul
