On Wednesday 12 March 2003 20:20, Todd Lyons wrote: > Todd Lyons wrote on Wed, Mar 12, 2003 at 10:35:13AM -0800 : > > > Processor #0 Pentium 4(tm) XEON(tm) APIC version 16 > > > ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled) > > > Processor #2 Pentium 4(tm) XEON(tm) APIC version 16 > > > ACPI: LAPIC (acpi_id[0x03] lapic_id[0x01] disabled) > > > ACPI: LAPIC (acpi_id[0x04] lapic_id[0x03] disabled) > > > ACPI: IOAPIC (id[0x02] address[0xfec00000] global_irq_base[0x0]) > > > > It's doing it here too. It's calling it CPU0 and CPU2 instead of > > CPU0 and CPU1. > > which Juan has already stated is normal. My bad for pointing out > something that was a red herring. But at the same time, I have to > wonder if the code for enabling local apic is designed to handle this > out of sequence numbering. I assume due to Juan's assertion that the > answer is yes. Also, Juan's answer was that it is normal for P4's to > route everything to one CPU which is suprising.
My guess is that CPU1 and CPU3 are slots for the two other processors when hyperthreading is enabled. However, the interrupt behavior does not change if hyperthreading is enabled. I wonder why with 9.0 kernel (.19-24) I see one and just one interrupt on the second cpu for ide channels, but nothing else. Teemu
