>>>>> "todd" == Todd Lyons <[EMAIL PROTECTED]> writes:
Hi >> For the APIC routing all interrupts to only one CPU, it is not normal. todd> I think that's what people are bugging about in the Cooker list at the todd> moment. I never noticed it until someone in the list mentioned it. The todd> complaint is that it's impacting performance, I personally have not seen todd> anything as a result of it. If you have lots of interrupts (think for instance of a network server), you will notice the drop in performance :( >> Notice that for P4, it is normal, as some designer decided that this >> was the right thing to do :( todd> Hmmm, so it's done for the P4 like that at the hardware level? todd> Interesting. Thanks for the In the P4 only way to fix it is to spread the interrupts by hand between the processors. Dual Pentium (<P4) use an algorithm that is a some special case of round robin. I don't remember the details, but basically was that each interrupt goes to each cpu in round robin order. Later, Juan. -- In theory, practice and theory are the same, but in practice they are different -- Larry McVoy
