serengeti.diff and dtc-links.diff make serengeti find all of its devices
correctly.
serengeti.diff
- takes out the multiple links for the Opteron (they weren't working
correctly)
- adds the 8132 devices and makes them pci_a so they don't conflict with the
8111
- corrects the disabled flags (I think we should have a build error
somewhere when there are incorrect flags)
- moves the lpc device to the lpc bus
- adds back in the second Opteron
Signed-off-by: Myles Watson <[email protected]>
dtc-links.diff
- removes multiple link code. I know someone could probably fix it, but
it's broken and not needed for now.
It made siblings that were bridges be multiple links on the same device.
That messed a lot of things up for Serengeti. I think it could be changed
so that siblings with the same PCI identifier that are bridges become
multiple links. It's ugly, though.
Signed-off-by: Myles Watson <[email protected]>
pci_match_v2.diff:
Even though Serengeti seems to work the same as v2, it still won't show
anything on the display. The VGA device is not claiming the 0xa0000-0xc0000
address space. Since SimNOW is a simulator, I trace the memory space to see
that the VGA writes are going to RAM.
I put this in to make the PCI config space bit-for-bit identical at VGA ROM
run. It still doesn't work. :( Any help would be appreciated.
Thanks,
Myles
Index: coreboot-v3/mainboard/amd/serengeti/dts
===================================================================
--- coreboot-v3.orig/mainboard/amd/serengeti/dts
+++ coreboot-v3/mainboard/amd/serengeti/dts
@@ -26,11 +26,24 @@
subsystem_device = "0x2b80";
cpus { };
a...@0 {
+ /config/("northbridge/amd/k8/apic");
};
dom...@0 {
/config/("northbridge/amd/k8/domain");
- p...@18,0 {
+ p...@18,0 {
/config/("northbridge/amd/k8/pci");
+ pc...@0,0 {
+ /config/("southbridge/amd/amd8132/pcix.dts");
+ };
+ pc...@0,1 {
+ /config/("southbridge/amd/amd8132/apic.dts");
+ };
+ pc...@1,0 {
+ /config/("southbridge/amd/amd8132/pcix.dts");
+ };
+ pc...@1,1 {
+ /config/("southbridge/amd/amd8132/apic.dts");
+ };
p...@0,0 {
/config/("southbridge/amd/amd8111/pci.dts");
p...@0,0{
@@ -41,15 +54,21 @@
};
p...@0,2{
/config/("southbridge/amd/amd8111/usb2.dts");
- disable;
+ disabled;
};
p...@1,0{
/config/("southbridge/amd/amd8111/nic.dts");
- disable;
+ disabled;
};
};
p...@1,0 {
/config/("southbridge/amd/amd8111/lpc.dts");
+ iop...@2e {
+ /config/("superio/winbond/w83627hf/dts");
+ kbenable = "1";
+ com1enable = "1";
+ hwmenable = "1";
+ };
};
p...@1,1 {
/config/("southbridge/amd/amd8111/ide.dts");
@@ -64,28 +83,27 @@
};
p...@1,5 {
/config/("southbridge/amd/amd8111/ac97audio.dts");
+ disabled;
};
p...@1,6 {
/config/("southbridge/amd/amd8111/ac97modem.dts");
+ disabled;
};
- p...@2,0 {
- /config/("southbridge/amd/amd8132/pcix.dts");
+ p...@1,7 {
};
};
- p...@18,0 {
- /config/("northbridge/amd/k8/pci");
+ p...@18,1 {};
+ p...@18,2 {};
+ p...@18,3 {
+ /config/("northbridge/amd/k8/mcf3");
};
- p...@18,0 {
+ p...@19,0 {
/config/("northbridge/amd/k8/pci");
};
- p...@18,1 {};
- p...@18,2 {};
- p...@18,3 {};
- };
- iop...@2e {
- /config/("superio/winbond/w83627hf/dts");
- kbenable = "1";
- com1enable = "1";
- hwmenable = "1";
+ p...@19,1 {};
+ p...@19,2 {};
+ p...@19,3 {
+ /config/("northbridge/amd/k8/mcf3");
+ };
};
};
Index: coreboot-v3/util/dtc/flattree.c
===================================================================
--- coreboot-v3.orig/util/dtc/flattree.c
+++ coreboot-v3/util/dtc/flattree.c
@@ -703,7 +703,7 @@ static void coreboot_emit_special(FILE *
* There is a good chance we could expand the for loop to contain this first bit of code.
* OTOH, the compiler can do it for us, and the initial conditions are clearer this way.
*/
- if ((! tree->linked) && is_bridge(tree)){
+ if (is_bridge(tree)){
struct node *siblings;
fprintf(f,"\t.link = {\n");
fprintf(f,"\t\t[%d] = {\n", linkcount);
@@ -714,24 +714,6 @@ static void coreboot_emit_special(FILE *
fprintf(f,"\t\t},\n");
/* now we need to handle our siblings. */
linkcount++;
- for_all_siblings(tree, siblings) {
- if (is_bridge(siblings) && (!siblings->linked)){
- fprintf(f,"\t\t[%d] = {\n", linkcount);
- fprintf(f,"\t\t\t.dev = &dev_%s,\n", siblings->label);
- fprintf(f,"\t\t\t.link = %d,\n", linkcount);
- if (siblings->children) {
- fprintf(f,"\t\t\t.children = &dev_%s\n", siblings->children->label);
- siblings->children->linked = 1;
- siblings->children->linknode = tree;
- siblings->children->whichlink = linkcount;
- }
- fprintf(f,"\t\t},\n");
- siblings->linked = 1;
- siblings->whichlink = linkcount;
- siblings->linknode = tree;
- linkcount++;
- }
- }
fprintf(f,"\t},\n");
}
fprintf(f,"\t.links = %d,\n", linkcount);
Index: coreboot-v3/device/device.c
===================================================================
--- coreboot-v3.orig/device/device.c
+++ coreboot-v3/device/device.c
@@ -1016,6 +1016,7 @@ void dev_phase4(void)
* highest addresses I can manage.
*/
mem->base = resource_max(&root->resource[1]);
+ mem->base = 0xfc000000;
mem->flags |= IORESOURCE_ASSIGNED;
mem->flags &= ~IORESOURCE_STORED;
Index: coreboot-v3/device/pci_device.c
===================================================================
--- coreboot-v3.orig/device/pci_device.c
+++ coreboot-v3/device/pci_device.c
@@ -725,9 +725,47 @@ void pci_dev_init(struct device *dev)
printk(BIOS_INFO, "Probing for option ROM\n");
rom = pci_rom_probe(dev);
+ printk(BIOS_INFO, "Probe returns %p\n",rom);
if (rom == NULL)
return;
ram = pci_rom_load(dev, rom);
+ printk(BIOS_INFO, "Load returns %p\n",ram);
+
+ /* This is for paranoia's sake */
+ pci_conf1_write_config32(PCI_BDF(0,0xa,0),0x28, 0x00000000);
+ pci_conf1_write_config32(PCI_BDF(0,0xa,0),0x2c, 0x00000000);
+ pci_conf1_write_config32(PCI_BDF(0,0xb,0),0x28, 0x00000000);
+ pci_conf1_write_config32(PCI_BDF(0,0xb,0),0x2c, 0x00000000);
+
+ pci_conf1_write_config32(PCI_BDF(0,0x18,0),0x6c, 0x00000270);
+
+ pci_conf1_write_config32(PCI_BDF(0,0x18,2),0x88, 0xdf004002);
+ pci_conf1_write_config32(PCI_BDF(0,0x18,2),0x94, 0x34009078);
+ pci_conf1_write_config32(PCI_BDF(0,0x18,2),0x98, 0xc0000030);
+ pci_conf1_write_config32(PCI_BDF(0,0x18,2),0xa0, 0xdf0020e9);
+
+ pci_conf1_write_config32(PCI_BDF(0,0x18,3),0x58, 0x00161616);
+ pci_conf1_write_config32(PCI_BDF(0,0x18,3),0x5c, 0x00030000);
+ pci_conf1_write_config32(PCI_BDF(0,0x18,3),0x5c, 0x00070000);
+ pci_conf1_write_config32(PCI_BDF(0,0x18,3),0x5c, 0x00030000);
+ pci_conf1_write_config32(PCI_BDF(0,0x18,3),0x80, 0x00000000);
+ pci_conf1_write_config32(PCI_BDF(0,0x18,3),0x84, 0x00000000);
+ pci_conf1_write_config32(PCI_BDF(0,0x18,3),0x90, 0x00000002);
+ pci_conf1_write_config32(PCI_BDF(0,0x18,3),0x94, 0x0000007c);
+ pci_conf1_write_config32(PCI_BDF(0,0x18,3),0xd4, 0x0000a000);
+ pci_conf1_write_config32(PCI_BDF(0,0x18,3),0xd8, 0x00000000);
+
+ pci_conf1_write_config16(PCI_BDF(0,0x6,0),0x4, 0x0107);
+ pci_conf1_write_config16(PCI_BDF(1,0x0,0),0x4, 0x0002);
+ pci_conf1_write_config16(PCI_BDF(1,0x0,1),0x4, 0x0002);
+ pci_conf1_write_config16(PCI_BDF(1,0x4,0),0x4, 0x0003);
+ pci_conf1_write_config16(PCI_BDF(1,0x5,0),0x4, 0x0003);
+
+ pci_conf1_write_config16(PCI_BDF(0,0x7,3),0x42, 0x2000);
+ pci_conf1_write_config16(PCI_BDF(0,0x7,3),0x70, 0x0000);
+ pci_conf1_write_config16(PCI_BDF(0,0x7,3),0x72, 0x0000);
+ pci_conf1_write_config16(PCI_BDF(0,0x7,3),0x74, 0x0000);
+
if (ram == NULL)
return;
run_bios(dev, (unsigned long)ram);
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
