On Thu, Dec 18, 2008 at 12:21 PM, Myles Watson <[email protected]> wrote:
>
>
> On Thu, Dec 18, 2008 at 11:51 AM, Myles Watson <[email protected]> wrote:
>
>>
>>
>> On Thu, Dec 18, 2008 at 11:41 AM, Marc Jones <[email protected]> wrote:
>>
>>> On Wed, Dec 17, 2008 at 1:42 PM, Myles Watson <[email protected]> wrote:
>>> > serengeti.diff and dtc-links.diff make serengeti find all of its
>>> devices
>>> > correctly.
>>> >
>>> > serengeti.diff
>>> > - takes out the multiple links for the Opteron (they weren't working
>>> > correctly)
>>> > - adds the 8132 devices and makes them pci_a so they don't conflict
>>> with the
>>> > 8111
>>> > - corrects the disabled flags (I think we should have a build error
>>> > somewhere when there are incorrect flags)
>>> > - moves the lpc device to the lpc bus
>>> > - adds back in the second Opteron
>>> >
>>> > Signed-off-by: Myles Watson <[email protected]>
>>> >
>>>
>>> Acked-by: Marc Jones <[email protected]>
>>> But what about amd8151?
>>
>>
I was thinking the 8151 was on a different link of the same Opteron. It's
not. Since it's on a different Opteron, it's easy. Sorry for the
confusion.
This patch adds the 8151 and makes it compile. Tested on the free version,
so the 8151 just gets disabled.
Signed-off-by: Myles Watson <[email protected]>
BTW: it still needs the dtc patch. If you don't have it, this adds yet
another case where two links are created instead of one.
Thanks,
Myles
Index: coreboot-v3/mainboard/amd/serengeti/dts
===================================================================
--- coreboot-v3.orig/mainboard/amd/serengeti/dts
+++ coreboot-v3/mainboard/amd/serengeti/dts
@@ -26,11 +26,24 @@
subsystem_device = "0x2b80";
cpus { };
a...@0 {
+ /config/("northbridge/amd/k8/apic");
};
dom...@0 {
/config/("northbridge/amd/k8/domain");
- p...@18,0 {
+ p...@18,0 {
/config/("northbridge/amd/k8/pci");
+ pc...@0,0 {
+ /config/("southbridge/amd/amd8132/pcix.dts");
+ };
+ pc...@0,1 {
+ /config/("southbridge/amd/amd8132/apic.dts");
+ };
+ pc...@1,0 {
+ /config/("southbridge/amd/amd8132/pcix.dts");
+ };
+ pc...@1,1 {
+ /config/("southbridge/amd/amd8132/apic.dts");
+ };
p...@0,0 {
/config/("southbridge/amd/amd8111/pci.dts");
p...@0,0{
@@ -41,15 +54,21 @@
};
p...@0,2{
/config/("southbridge/amd/amd8111/usb2.dts");
- disable;
+ disabled;
};
p...@1,0{
/config/("southbridge/amd/amd8111/nic.dts");
- disable;
+ disabled;
};
};
p...@1,0 {
/config/("southbridge/amd/amd8111/lpc.dts");
+ iop...@2e {
+ /config/("superio/winbond/w83627hf/dts");
+ kbenable = "1";
+ com1enable = "1";
+ hwmenable = "1";
+ };
};
p...@1,1 {
/config/("southbridge/amd/amd8111/ide.dts");
@@ -64,28 +83,34 @@
};
p...@1,5 {
/config/("southbridge/amd/amd8111/ac97audio.dts");
+ disabled;
};
p...@1,6 {
/config/("southbridge/amd/amd8111/ac97modem.dts");
+ disabled;
};
- p...@2,0 {
- /config/("southbridge/amd/amd8132/pcix.dts");
+ p...@1,7 {
};
};
- p...@18,0 {
- /config/("northbridge/amd/k8/pci");
+ p...@18,1 {};
+ p...@18,2 {};
+ p...@18,3 {
+ /config/("northbridge/amd/k8/mcf3");
};
- p...@18,0 {
+ p...@19,0 {
/config/("northbridge/amd/k8/pci");
};
- p...@18,1 {};
- p...@18,2 {};
- p...@18,3 {};
- };
- iop...@2e {
- /config/("superio/winbond/w83627hf/dts");
- kbenable = "1";
- com1enable = "1";
- hwmenable = "1";
+ p...@19,1 {
+ p...@0,0 {
+ /config/("southbridge/amd/amd8151/agpbridge.dts");
+ };
+ p...@1,0 {
+ /config/("southbridge/amd/amd8151/agpdev.dts");
+ };
+ };
+ p...@19,2 {};
+ p...@19,3 {
+ /config/("northbridge/amd/k8/mcf3");
+ };
};
};
Index: coreboot-v3/mainboard/amd/Kconfig
===================================================================
--- coreboot-v3.orig/mainboard/amd/Kconfig
+++ coreboot-v3/mainboard/amd/Kconfig
@@ -67,6 +67,7 @@ config BOARD_AMD_SERENGETI
select NORTHBRIDGE_AMD_K8
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8132
+ select SOUTHBRIDGE_AMD_AMD8151
select SUPERIO_WINBOND_W83627HF
select IOAPIC
help
Index: coreboot-v3/Kconfig
===================================================================
--- coreboot-v3.orig/Kconfig
+++ coreboot-v3/Kconfig
@@ -104,6 +104,8 @@ config SOUTHBRIDGE_INTEL_I82371EB
boolean
config SOUTHBRIDGE_NVIDIA_MCP55
boolean
+config SOUTHBRIDGE_AMD_AMD8151
+ boolean
config SOUTHBRIDGE_AMD_AMD8132
boolean
config SOUTHBRIDGE_AMD_AMD8111
Index: coreboot-v3/mainboard/amd/serengeti/defconfig
===================================================================
--- coreboot-v3.orig/mainboard/amd/serengeti/defconfig
+++ coreboot-v3/mainboard/amd/serengeti/defconfig
@@ -113,6 +113,7 @@ CONFIG_HW_MEM_HOLE_SIZEK=0x1000
CONFIG_NORTHBRIDGE_AMD_K8=y
CONFIG_SOUTHBRIDGE_AMD_AMD8111=y
CONFIG_SOUTHBRIDGE_AMD_AMD8132=y
+CONFIG_SOUTHBRIDGE_AMD_AMD8151=y
CONFIG_SUPERIO_WINBOND_W83627HF=y
#
Index: coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c
===================================================================
--- coreboot-v3.orig/southbridge/amd/amd8151/amd8151_agp3.c
+++ coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c
@@ -25,7 +25,6 @@
#include <device/pci_ids.h>
#include <statictree.h>
#include <config.h>
-#include "mcp55.h"
static void agp3bridge_init(struct device * dev)
{
@@ -45,7 +44,7 @@ struct device_operations amd8151_agp3bri
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_8151_AGP}}},
.constructor = default_device_constructor,
- .phase3_scan = pci_scan_bridge
+ .phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
@@ -80,7 +79,7 @@ struct device_operations amd8151_agp3dev
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_8151_SYSCTRL}}},
.constructor = default_device_constructor,
- .phase4_enable_disable = agp3dev_enable,
+ .phase3_enable = agp3dev_enable,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
--
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