We do have an US-III/IV optimized AES implementation, but that has nothing to do with this byte order swapping business.
I think the gains for the byte order swapping should be similar (in percentage) for the US II/III/IV processors, but might be different for the T1/T2 family, that is why I asked. Ferenc Garrett D'Amore wrote: > Dan Anderson wrote: > >> On Thu, 28 Aug 2008, Ferenc Rakoczi wrote: >> >> >>> The changes look good. For the >>> SPARC version, the '& 0xff000000' part for the >>> 32-bit version and the '& 0xff00000000000000ULL' >>> for the 64-bit version and the '& 0xff' for both >>> versions can be omitted (though I think at -xO3 >>> or greater level of optimization the compiler will >>> not emit any instruction for those anyways). >>> >>> >> Great idea--I removed those masks. >> >> >> >>> Just out of curiosity, what type of processor was >>> used for the SPARC results on your spreadsheet? >>> Thanks, >>> Ferenc >>> >>> >> thrace.sfbay: sun4u, Sun Fire V120, UltraSPARC-IIe (648 MHz), 1GB memory >> Not fast or new, but I don't have to worry about anyone else wanting to use >> it. >> It shouldn't be used for comparison with x86, just a before/after comparison >> with itself. >> >> > > I thought at one point we had a version of AES that was optmized for > US-IIIi and higher processors. Is that not the case? (If it is, it > might be worthwhile to do a test run on US-IIIi hardware.) > > -- Garrett > >> -- >> This message posted from opensolaris.org >> _______________________________________________ >> crypto-discuss mailing list >> crypto-discuss at opensolaris.org >> http://mail.opensolaris.org/mailman/listinfo/crypto-discuss >> >> > > _______________________________________________ > crypto-discuss mailing list > crypto-discuss at opensolaris.org > http://mail.opensolaris.org/mailman/listinfo/crypto-discuss >
