No, I didn't but my outsourcers did it. 1) SPIDELAY is configured as shown below:
SPIDELAY |= (0xF << 24); // maximum setup time SPIDELAY |= (0xF << 16); // maximum hold time 2) SPIFMT0 is configuread as: SPI_LSB_FIRST | SPI_PHASE_NORMAL | SPI_CLOCK_LOW | SPI_CLOCK_SCALE(0xFF) | SPI_DATA_LENGTH(8) Where #define SPI_MSB_FIRST (1<<20) #define SPI_LSB_FIRST (0<<20) #define SPI_CLOCK_LOW (0<<17) #define SPI_CLOCK_HIGH (1<<17) #define SPI_PHASE_NORMAL (0<<16) #define SPI_PHASE_CLOCK_DELAY (1<<16) #define SPI_CLOCK_SCALE(s) (((s)&0xFF)<<8) #define SPI_DATA_LENGTH(l) (8) // currently hardcoded to 8 3) Do you know maybe TI supplies examples for SPI controller which shows how to communicate with SPI slave (SPI EEPROM or smth like this)? I need to hold CS active during data transfer... Regards, Kirill -----Original Message----- From: Carlos Ojea [mailto:[EMAIL PROTECTED] Sent: Monday, November 27, 2006 4:14 PM To: Kirill Sukhonosenko Cc: [email protected] Subject: Re: SPI issue Did you write your SPI driver yourself? Maybe SPIFMT0 or SPIDELAY are not properly configured. Where are you configuring SPI registers? Regards, Carlos _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
