SPIDELAY |= (0xF << 24); // maximum setup time SPIDELAY |= (0xF << 16); // maximum hold time
I am using 0 for these two.
3) Do you know maybe TI supplies examples for SPI controller which shows how to communicate with SPI slave (SPI EEPROM or smth like this)? I need to hold CS active during data transfer...
I don't know. I only configure spi registers and transmit writing to SPIDAT1 and then waiting for TXFULL bit in SPIBUF register. Things seem to be ok, although I didn't test the transmission too much. Could the problem be the SPIDELAY ? Regards, Carlos _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
