Hi! I finally tried to setup SPI according to data sheet (SPRUE32) but I think data sheet is wrong. It states (see below) that configuration should be done while in reset mode (SPIGCR0: RESET bit). But it doesn't work. Only if you set RESET you can change registers.
I am a bit confused by this. And I'd like to ask if some one can provide me with correct configuration code sample or corrected document version... ----- Initializing the SPI Peripheral When Chip Selects are Used (4-pin Mode) Make sure the SPI module is in reset by clearing the RESET bit in the SPI global control (SPIGCR0) to 0. Enable the CLKMOD and MASTER bits in the SPI global control register 1 (SPIGCR1). Enable the SPI_DI, SPI_DO, and SPI_CLK pins and the necessary chip select pins SPI_EN1) by setting the corresponding bits in the SPI pin control register (SPIPC0). Configure the desired data format in the SPI data format register (SPIFMTn). a. Program the clock prescale value in the PRESCALEn bit. b. Program the character size in the CHARLENn bit. c. Set the SPI clock PHASEn and POLARITYn bits. d. Set the shift direction in the SHIFTDIRn bit. Select the preconfigured data format using the DFSEL bit in the SPI shift register ( If needed, configure the setup or hold time for the chip select lines using the C2TDELAY T2CDELAY bits in the SPI delay register (SPIDELAY). Select the desired chip select number. The CSNR field in SPIDAT1 defines the chip activated during the data transfer. Note that the SPI_ENn signals are active low. Setup the default chip select pin value when chip select lines are inactive using the SPI default chip select register (SPIDEF). Enable the desired interrupts, if any, in the SPI interrupt register (SPIINT). 10. Select whether you want the interrupt events mapped to INT0 or INT1 using the RXINTLVL SPI interrupt level register (SPILVL). 11. Remove the SPI peripheral from reset by setting the RESET bit in SPIGCR0. 12. If using the EDMA to perform the transfers, setup and enable the EDMA channels receive and then set the DMAREQEN bit in SPIINT. 13. Enable the SPIENA bit in SPIGCR1. 14. Data is ready to be transferred using the CPU or EDMA by writing to SPIDAT1. --- Regards, Kirill -----Original Message----- From: Carlos Ojea [mailto:[EMAIL PROTECTED] Sent: Monday, November 27, 2006 6:29 PM To: Kirill Sukhonosenko Cc: [email protected] Subject: Re: SPI issue > SPIDELAY |= (0xF << 24); // maximum setup time > SPIDELAY |= (0xF << 16); // maximum hold time I am using 0 for these two. > 3) Do you know maybe TI supplies examples for SPI controller which shows how > to communicate with SPI slave (SPI EEPROM or smth like this)? I need to hold > CS active during data transfer... I don't know. I only configure spi registers and transmit writing to SPIDAT1 and then waiting for TXFULL bit in SPIBUF register. Things seem to be ok, although I didn't test the transmission too much. Could the problem be the SPIDELAY ? Regards, Carlos _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
