Hi,
This is more of a Linux question than anything. Hopefully someone can help me.
Our custom board has the Davinci exchanging data with a Xilinx Virtex 5 Pro
FPGA Microblaze processor via a shared (Dual-Port) RAM interface. The shared
RAM is 128Kb and is hooked us to CS4 on the AEMIF. In order to access this
shared RAM memory space (physical address is 0x06000000), our application is
using mmap to map it to a virtual address space. Here's a snippet of the mmap
initialization:
int fd;
unsigned char *shareRamPtr;
fd = open("/dev/mem", O_RDWR);
sharedRamPtr = (unsigned char *)mmap(0, 0x20000 /* 128 Kb */, PROT_READ |
PROT_WRITE,
MAP_SHARED, fd, 0x06000000);
It seems to work but not quite. We have a interrupt processing handler that
needs access (writes as well as reads) this space in real-time every 2ms.
Sometimes, when the FPGA Microblaze write values to the shared RAM, and when
our ARM processor on the Davinci reads them during the interrupt processing,
the data looks staled (as though from previous reads). I googled and found
that writes require a call to msync to flush writes to the actual shared RAM
interface. So here are my questions:
1) If I need the writes to be real-time (immediately flushed out to the shared
RAM), do I have to call msync every single time I do a write? If this is the
case, isn't this very inefficient? Does msync have to check the whole 0x20000
range to check what bytes need to be flushed?
2) How about for reads? As mentioned above, I seem to get stale data sometimes
during reads. Since the Microblaze is constantly writing to shared RAM, what
needs to be done so that when the ARM reads the data at those locations, they
are what the Microblaze wrote?
3) I tried using MAP_PRIVATE and it doesn't seem to map to the shared RAM space
at all (mmap doesn't return an error but I can't write or read from it). Is
there anyway to force the mechanism behind mmap (driver for /dev/mem ?) to
force a flush everytime the ARM writes to shared RAM without having to call
msync?
Please advise. Thanks.
Regards,
Andy
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