R. Simning wrote:
Andy Ngo wrote:
..... the FPGA Microblaze write values to the shared RAM, and when
our ARM processor on the Davinci reads them during the interrupt
processing, the data looks staled (as though from previous reads).
...
I thought the declaration of a variable as "volatile" would force the
value to always be read directly from RAM, never cache. I'm not clear
whether declaring a variable "volatile" forces the write to RAM, but
that case doesn't seem to be an issue here.
I would believe that just declaring those data structures as
"volatile" should resolve your cache issues of reading "stale" data.
No, that only tells the compiler not to optimize-out references to a
variable, always fetching a new value from "memory" when necessary. The
compiler has no knowledge if the value is fetched from actual memory,
from an internal or external cache, or if it is out of sync with a
second CPU's view, etc.
We went through the same problem recently, one of my colleagues found
the answer:
(a) Declare all variables in the mapped area as volatile, and
(b) Do a readback immediately after writing to mapped memory, to force
flushing the cache.
See http://www.arm.com/pdfs/DDI0198D_926_TRM.pdf, chapter 4, in
particular section 4.2, for the rationale behind this.
Roberto Waltman
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