Also, rename a few of the not-yet-used clocks to lowercase.
Signed-off-by: Kevin Hilman <[email protected]>
---
Depends on previous clock/pll patches now in Davinci git.
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 8286753..1b796bf 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -47,47 +47,59 @@ static struct clk pll1_clk = {
.pll_data = &pll1_data,
};
-static struct clk pll2_clk = {
- .name = "pll2",
- .parent = &ref_clk,
- .flags = CLK_PLL,
- .pll_data = &pll2_data,
-};
-
static struct clk aux_clk = {
.name = "aux_clk",
.parent = &ref_clk,
.flags = CLK_PLL,
};
-static struct clk sysclk1_clk = {
- .name = "SYSCLK1",
+static struct clk pll1_sysclk1 = {
+ .name = "pll1_sysclk1",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV1,
};
-static struct clk sysclk2_clk = {
- .name = "SYSCLK2",
+static struct clk pll1_sysclk2 = {
+ .name = "pll1_sysclk2",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV2,
};
-static struct clk vpbe_clk = { /* a.k.a. PLL1.SYSCLK3 */
- .name = "vpbe",
+static struct clk pll1_sysclk3 = {
+ .name = "pll1_sysclk3",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV3,
};
-static struct clk vpss_clk = { /* a.k.a. PLL1.SYCLK4 */
- .name = "vpss",
+static struct clk pll1_sysclk4 = {
+ .name = "pll1_sysclk4",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV4,
};
+static struct clk pll1_sysclkbp = {
+ .name = "pll1_sysclkbp",
+ .parent = &pll1_clk,
+ .flags = CLK_PLL,
+ .div_reg = BPDIV
+};
+
+static struct clk vpbe_clk = {
+ .name = "vpbe",
+ .parent = &pll1_sysclk3,
+ .flags = CLK_PLL,
+};
+
+static struct clk vpss_clk = {
+ .name = "vpss",
+ .parent = &pll1_sysclk4,
+ .flags = CLK_PLL,
+};
+
static struct clk clkout1_clk = {
.name = "clkout1",
.parent = &aux_clk,
@@ -95,11 +107,31 @@ static struct clk clkout1_clk = {
/* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
};
-static struct clk clkout2_clk = { /* a.k.a. PLL1.SYSCLKBP */
+static struct clk clkout2_clk = {
.name = "clkout2",
- .parent = &pll1_clk,
+ .parent = &pll1_sysclkbp,
.flags = CLK_PLL,
- .div_reg = BPDIV,
+};
+
+static struct clk pll2_clk = {
+ .name = "pll2",
+ .parent = &ref_clk,
+ .flags = CLK_PLL,
+ .pll_data = &pll2_data,
+};
+
+static struct clk pll2_sysclk1 = {
+ .name = "pll2_sysclk1",
+ .parent = &pll2_clk,
+ .flags = CLK_PLL,
+ .div_reg = PLLDIV1,
+};
+
+static struct clk pll2_sysclkbp = {
+ .name = "pll2_sysclkbp",
+ .parent = &pll2_clk,
+ .flags = CLK_PLL,
+ .div_reg = BPDIV
};
static struct clk clkout3_clk = {
@@ -112,7 +144,7 @@ static struct clk clkout3_clk = {
static struct clk arm_clk = {
.name = "ARMCLK",
- .parent = &sysclk1_clk,
+ .parent = &pll1_sysclk1,
.flags = ALWAYS_ENABLED | CLK_PLL,
};
@@ -144,7 +176,7 @@ static struct clk arm_clk = {
static struct clk mjcp_clk = {
.name = "mjcp",
- .parent = &sysclk1_clk,
+ .parent = &pll1_sysclk1,
.lpsc = DAVINCI_LPSC_IMCOP,
};
@@ -162,7 +194,7 @@ static struct clk uart1_clk = {
static struct clk uart2_clk = {
.name = "uart2",
- .parent = &sysclk2_clk,
+ .parent = &pll1_sysclk2,
.lpsc = DAVINCI_LPSC_UART2,
};
@@ -174,78 +206,78 @@ static struct clk i2c_clk = {
static struct clk asp0_clk = {
.name = "asp0_clk",
- .parent = &sysclk2_clk,
+ .parent = &pll1_sysclk2,
.lpsc = DAVINCI_LPSC_McBSP,
};
static struct clk asp1_clk = {
.name = "asp1_clk",
- .parent = &sysclk2_clk,
+ .parent = &pll1_sysclk2,
.lpsc = DM355_LPSC_McBSP1,
};
static struct clk mmcsd0_clk = {
.name = "MMCSDCLK0",
- .parent = &sysclk2_clk,
+ .parent = &pll1_sysclk2,
.lpsc = DAVINCI_LPSC_MMC_SD,
};
static struct clk mmcsd1_clk = {
.name = "MMCSDCLK1",
- .parent = &sysclk2_clk,
+ .parent = &pll1_sysclk2,
.lpsc = DM355_LPSC_MMC_SD1,
};
static struct clk spi0_clk = {
.name = "SPICLK",
- .parent = &sysclk2_clk,
+ .parent = &pll1_sysclk2,
.lpsc = DAVINCI_LPSC_SPI,
};
static struct clk spi1_clk = {
.name = "SPICLK1",
- .parent = &sysclk2_clk,
+ .parent = &pll1_sysclk2,
.lpsc = DM355_LPSC_SPI1,
};
static struct clk spi2_clk = {
.name = "SPICLK2",
- .parent = &sysclk2_clk,
+ .parent = &pll1_sysclk2,
.lpsc = DM355_LPSC_SPI2,
};
static struct clk gpio_clk = {
.name = "gpio",
- .parent = &sysclk2_clk,
+ .parent = &pll1_sysclk2,
.lpsc = DAVINCI_LPSC_GPIO,
};
static struct clk aemif_clk = {
- .name = "AEMIFCLK",
- .parent = &sysclk2_clk,
+ .name = "aemif",
+ .parent = &pll1_sysclk2,
.lpsc = DAVINCI_LPSC_AEMIF,
.usecount = 1,
};
static struct clk pwm0_clk = {
- .name = "PWM0_CLK",
+ .name = "pwm0",
.parent = &aux_clk,
.lpsc = DAVINCI_LPSC_PWM0,
};
static struct clk pwm1_clk = {
- .name = "PWM1_CLK",
+ .name = "pwm1",
.parent = &aux_clk,
.lpsc = DAVINCI_LPSC_PWM1,
};
static struct clk pwm2_clk = {
- .name = "PWM2_CLK",
+ .name = "pwm2",
.parent = &aux_clk,
.lpsc = DAVINCI_LPSC_PWM2,
};
static struct clk pwm3_clk = {
- .name = "PWM3_CLK",
+ .name = "pwm3",
.parent = &aux_clk,
.lpsc = DM355_LPSC_PWM3,
};
@@ -276,7 +308,7 @@ static struct clk timer3_clk = {
static struct clk usb_clk = {
.name = "USBCLK",
- .parent = &sysclk2_clk,
+ .parent = &pll1_sysclk2,
.lpsc = DAVINCI_LPSC_USB,
};
@@ -284,13 +316,18 @@ static struct clk *dm355_clks[] __initdata = {
&ref_clk,
&pll1_clk,
&aux_clk,
- &sysclk1_clk,
- &sysclk2_clk,
+ &pll1_sysclk1,
+ &pll1_sysclk2,
+ &pll1_sysclk3,
+ &pll1_sysclk4,
+ &pll1_sysclkbp,
&vpbe_clk,
&vpss_clk,
&clkout1_clk,
&clkout2_clk,
&pll2_clk,
+ &pll2_sysclk1,
+ &pll2_sysclkbp,
&clkout3_clk,
&arm_clk,
&mjcp_clk,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 680b1dd..e331090 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -44,44 +44,65 @@ static struct clk pll1_clk = {
.flags = CLK_PLL,
};
-static struct clk pll2_clk = {
- .name = "pll2",
- .parent = &ref_clk,
- .pll_data = &pll2_data,
- .flags = CLK_PLL,
-};
-
-static struct clk sysclk1_clk = {
- .name = "SYSCLK1",
+static struct clk pll1_sysclk1 = {
+ .name = "pll1_sysclk1",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV1,
};
-static struct clk sysclk2_clk = {
- .name = "SYSCLK2",
+static struct clk pll1_sysclk2 = {
+ .name = "pll1_sysclk2",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV2,
};
-static struct clk sysclk3_clk = {
- .name = "SYSCLK3",
+static struct clk pll1_sysclk3 = {
+ .name = "pll1_sysclk3",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV3,
};
-static struct clk sysclk5_clk = {
- .name = "SYSCLK5",
+static struct clk pll1_sysclk5 = {
+ .name = "pll1_sysclk5",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV5,
};
+static struct clk pll2_clk = {
+ .name = "pll2",
+ .parent = &ref_clk,
+ .pll_data = &pll2_data,
+ .flags = CLK_PLL,
+};
+
+static struct clk pll2_sysclk1 = {
+ .name = "pll2_sysclk1",
+ .parent = &pll2_clk,
+ .flags = CLK_PLL,
+ .div_reg = PLLDIV1,
+};
+
+static struct clk pll2_sysclk2 = {
+ .name = "pll2_sysclk2",
+ .parent = &pll2_clk,
+ .flags = CLK_PLL,
+ .div_reg = PLLDIV2,
+};
+
+static struct clk pll2_sysclkbp = {
+ .name = "pll2_sysclkbp",
+ .parent = &pll2_clk,
+ .flags = CLK_PLL,
+ .div_reg = BPDIV
+};
+
static struct clk arm_clk = {
- .name = "ARMCLK",
- .parent = &sysclk2_clk,
+ .name = "arm",
+ .parent = &pll1_sysclk2,
.lpsc = DAVINCI_LPSC_NONE,
.flags = ALWAYS_ENABLED,
};
@@ -106,7 +127,7 @@ static struct clk uart2_clk = {
static struct clk emac_clk = {
.name = "EMACCLK",
- .parent = &sysclk5_clk,
+ .parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
};
@@ -118,49 +139,49 @@ static struct clk i2c_clk = {
static struct clk ide_clk = {
.name = "IDECLK",
- .parent = &sysclk5_clk,
+ .parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_ATA,
};
static struct clk asp_clk = {
.name = "asp0_clk",
- .parent = &sysclk5_clk,
+ .parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_McBSP,
};
static struct clk mmcsd_clk = {
.name = "MMCSDCLK",
- .parent = &sysclk5_clk,
+ .parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_MMC_SD,
};
static struct clk spi_clk = {
- .name = "SPICLK",
- .parent = &sysclk5_clk,
+ .name = "spi",
+ .parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_SPI,
};
static struct clk gpio_clk = {
.name = "gpio",
- .parent = &sysclk5_clk,
+ .parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_GPIO,
};
static struct clk usb_clk = {
.name = "USBCLK",
- .parent = &sysclk5_clk,
+ .parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_USB,
};
static struct clk vlynq_clk = {
.name = "VLYNQCLK",
- .parent = &sysclk5_clk,
+ .parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_VLYNQ,
};
static struct clk aemif_clk = {
- .name = "AEMIFCLK",
- .parent = &sysclk5_clk,
+ .name = "aemif",
+ .parent = &pll1_sysclk5,
.lpsc = DAVINCI_LPSC_AEMIF,
.flags = ALWAYS_ENABLED,
};
@@ -186,11 +207,13 @@ static struct clk timer2_clk = {
static struct clk *dm644x_clks[] __initdata = {
&ref_clk,
&pll1_clk,
+ &pll1_sysclk1,
+ &pll1_sysclk2,
+ &pll1_sysclk3,
+ &pll1_sysclk5,
&pll2_clk,
- &sysclk1_clk,
- &sysclk2_clk,
- &sysclk3_clk,
- &sysclk5_clk,
+ &pll2_sysclk1,
+ &pll2_sysclk2,
&arm_clk,
&uart0_clk,
&uart1_clk,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 3f54872..1a2a947 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -52,79 +52,86 @@ static struct clk pll1_clk = {
.flags = CLK_PLL,
};
-static struct clk pll2_clk = {
- .name = "pll2",
- .parent = &ref_clk,
- .pll_data = &pll2_data,
- .flags = CLK_PLL,
-};
-
-static struct clk sysclk1_clk = {
- .name = "SYSCLK1",
+static struct clk pll1_sysclk1 = {
+ .name = "pll1_sysclk1",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV1,
};
-static struct clk sysclk2_clk = {
- .name = "SYSCLK2",
+static struct clk pll1_sysclk2 = {
+ .name = "pll1_sysclk2",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV2,
};
-static struct clk sysclk3_clk = {
- .name = "SYSCLK3",
+static struct clk pll1_sysclk3 = {
+ .name = "pll1_sysclk3",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV3,
};
-static struct clk sysclk4_clk = {
- .name = "SYSCLK4",
+static struct clk pll1_sysclk4 = {
+ .name = "pll1_sysclk4",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV4,
};
-static struct clk sysclk5_clk = {
- .name = "SYSCLK5",
+static struct clk pll1_sysclk5 = {
+ .name = "pll1_sysclk5",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV5,
};
-static struct clk sysclk6_clk = {
- .name = "SYSCLK6",
+static struct clk pll1_sysclk6 = {
+ .name = "pll1_sysclk6",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV6,
};
-static struct clk sysclk8_clk = {
- .name = "SYSCLK8",
+static struct clk pll1_sysclk8 = {
+ .name = "pll1_sysclk8",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV8,
};
-static struct clk sysclk9_clk = {
- .name = "SYSCLK9",
+static struct clk pll1_sysclk9 = {
+ .name = "pll1_sysclk9",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = PLLDIV9,
};
-static struct clk sysclkbp_clk = {
- .name = "SYSCLKBP",
+static struct clk pll1_sysclkbp = {
+ .name = "pll1_sysclkBP",
.parent = &pll1_clk,
.flags = CLK_PLL,
.div_reg = BPDIV,
};
+static struct clk pll2_clk = {
+ .name = "pll2_clk",
+ .parent = &ref_clk,
+ .pll_data = &pll2_data,
+ .flags = CLK_PLL,
+};
+
+static struct clk pll2_sysclk1 = {
+ .name = "pll2_sysclk1",
+ .parent = &pll2_clk,
+ .flags = CLK_PLL,
+ .div_reg = PLLDIV1,
+};
+
static struct clk arm_clk = {
- .name = "ARMCLK",
- .parent = &sysclk2_clk,
+ .name = "arm",
+ .parent = &pll1_sysclk2,
.lpsc = DAVINCI_LPSC_NONE,
.flags = ALWAYS_ENABLED,
};
@@ -149,54 +156,55 @@ static struct clk uart2_clk = {
static struct clk i2c_clk = {
.name = "I2CCLK",
- .parent = &sysclk3_clk,
+ .parent = &pll1_sysclk3,
.lpsc = DM646X_LPSC_I2C,
};
static struct clk gpio_clk = {
.name = "gpio",
- .parent = &sysclk3_clk,
+ .parent = &pll1_sysclk3,
.lpsc = DM646X_LPSC_GPIO,
};
static struct clk aemif_clk = {
- .name = "AEMIFCLK",
- .parent = &sysclk3_clk,
+ .name = "aemif",
+ .parent = &pll1_sysclk3,
.lpsc = DM646X_LPSC_AEMIF,
.flags = ALWAYS_ENABLED,
};
static struct clk emac_clk = {
.name = "EMACCLK",
- .parent = &sysclk3_clk,
+ .parent = &pll1_sysclk3,
.lpsc = DM646X_LPSC_EMAC,
};
static struct clk timer0_clk = {
.name = "timer0",
- .parent = &sysclk3_clk,
+ .parent = &pll1_sysclk3,
.lpsc = DM646X_LPSC_TIMER0,
};
static struct clk timer1_clk = {
.name = "timer1",
- .parent = &sysclk3_clk,
+ .parent = &pll1_sysclk3,
.lpsc = DM646X_LPSC_TIMER1,
};
static struct clk *dm646x_clks[] __initdata = {
&ref_clk,
&pll1_clk,
- &sysclk1_clk,
- &sysclk2_clk,
- &sysclk3_clk,
- &sysclk4_clk,
- &sysclk5_clk,
- &sysclk6_clk,
- &sysclk8_clk,
- &sysclk9_clk,
- &sysclkbp_clk,
+ &pll1_sysclk1,
+ &pll1_sysclk2,
+ &pll1_sysclk3,
+ &pll1_sysclk4,
+ &pll1_sysclk5,
+ &pll1_sysclk6,
+ &pll1_sysclk8,
+ &pll1_sysclk9,
+ &pll1_sysclkbp,
&pll2_clk,
+ &pll2_sysclk1,
&arm_clk,
&uart0_clk,
&uart1_clk,
--
1.6.1
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