David Brownell <[email protected]> writes: [...]
> > NOTE: on dm355, sysclkbp values (for both PLLs) are incorrect. > I changed the sysclkbp calculations recently because of what I understood of the spec. According to the doc I'm reading (dm355: sprs463e, revised july 2008, in particular Figure 3.3), SYSCLKBP comes out of the pll before the multiplier and dividers, ans is only affected by BPDIV. It looks the same for the other devices too. So, on my board I see pll1_sysclkbp = 8MHz, which is correct with ref_clk = 24MHz and PLL1.BPDIV = 3. For PLL2, I see 3MHz which looks correct for PLL2.BPDIV = 8. Kevin _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
