On Friday 30 January 2009, Kevin Hilman wrote: > > NOTE: on dm355, sysclkbp values (for both PLLs) are incorrect. > > > > I changed the sysclkbp calculations recently because of what I > understood of the spec. According to the doc I'm reading (dm355: > sprs463e, revised july 2008, in particular Figure 3.3), SYSCLKBP comes > out of the pll before the multiplier and dividers, ans is only > affected by BPDIV. It looks the same for the other devices too.
OK, that's correct then. Agrees with sprufb3, which is what I'm looking at, fig 6-1 ... the PLLC1 configuration picture gives a slightly different (more detailed/accurate) story than the device clocking picture (fig 5-1), which just shows that as a PLL output. Both AUXCLK and SYSCLKBP get taps *before* the PLL. If you want to make the time, the pll1_aux clocks could stand to be parented from the PLL with the same kind of special casing. > So, on my board I see pll1_sysclkbp = 8MHz, which is correct with > ref_clk = 24MHz and PLL1.BPDIV = 3. For PLL2, I see 3MHz which > looks correct for PLL2.BPDIV = 8. Whereas if it were PLL1/3 and PLL2/8 it'd be off by a lot, and that's what i was reacting to. Sorry for the false alarm. - Dave _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
