Alister
My understanding is the the 386 was a CISC the 486 introduced a RISC
instruction set, For what it is worth you may consider a CISC instruction as
a series of RISC instructions (microcode) in fact this is how they are implemented
Neven MacEwan (B.E. E&E) Ph. 09 621 0001 Mob. 0274 749062
Alister Christie wrote:
CPUs are so complicated these days. Modern Intel/AMD CPUs have the outward appearance of a CISC design, but I think that they are RISC internally. Someone correct me if I'm wrong, the last CPU that I actually knew much about was the Pentium Pro and I've forgotten most of that. I remember a major issue with the Pentium Pro in that when it encountered a 16 bit instruction it had to flush it's pipeline(s), which is why it was so bad for Win95 (those were the days - may they never return).
Alister Christie Computers for People Ph: 04 471 1849 Fax: 04 471 1266 http://www.salespartner.co.nz PO Box 13085 Johnsonville Wellington
Dennis Chuah wrote:
In Pentium CPU's all 8-, 16- or 32-bit operations are performed in one CPU
cycle, so there is no performance penalty. What you might be thinking of
are MOV operations involving non-aligned 16- and 32-bit data. In this case,
the performance penalty is one CPU read or write cycle - which can vary in
time depending on whether the data is cached or not.
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