Jens-Heiner Rechtien <[EMAIL PROTECTED]> writes:
> BTW, on newer processors (P4, Xeon etc) the "lock" prefix shouldn't be
> that expensive, because if the target memory of the instruction is
> cacheable the CPU will not assert the Lock# signal (which locks the
> bus) but only lock the affected cache line.
>
Wasn't Stephan's original measurement based on a P4 ("model name:
Intel(R) Pentium(R) 4 CPU 1.80GHz"), with a factor-eight slowdown?
So, how to go forward from here? Is anybody trying out/profiling the
proposed changes (switch on multi-coreness, inlining)?
Cheers,
--
Thorsten
If you're not failing some of the time, you're not trying hard enough.
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