I'm modelling a device that outputs 32 channels each 12 bits wide and I would like to create Migen construct that would synthesise to something like:
module top_level(
output reg [11:0] out_channels [31:0],
input sys_clk,
input sys_rst
);
I would assume Migen 'Array' comes to this but I cannot figure this out...
wbr Kusti
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