On Tuesday, January 30, 2018 09:10 PM, Kustaa Nyholm wrote:
module top_level(
output reg [11:0] out_channels [31:0],
That's not supported (do synthesizers even deal with this correctly or try to generate a memory?). You can create 12 signals instead...
I would assume Migen 'Array' comes to this but I cannot figure this out...
No, that's not what it does. Sébastien _______________________________________________ M-Labs devel mailing list https://ssl.serverraum.org/lists/listinfo/devel
