On 30/01/2018 19:50, "Guy Hutchison" <ghutc...@gmail.com> wrote:
>I believe you would need SystemVerilog syntax for this to work: > output reg [11:0][31:0] out_channels, Right, well System Verilog should be supported by Altera Quartus tools. What I was looking for was the 'array of multi-bit elements' reg [M:0] out_channels [0:N] not reg [11:0][31:0] out_channels which I think is a 2D array of 1 bit elements. Not that I'm very well versed in Verilog so this is just googled up stuff. >Packed structs and two-dimensional vectors are synthesizable with ASIC tools. >The Migen backend doesn't support this but you can easily create a vector of >signals: > > > out_channels = [Signal(12) for x in range(32)] > self.io.update(out_channels) Ok, thanks for the snippet just the thing I'm looking for, like I wrote in response to Sebestiens response, I had not thought about 'dynamically' creating them (as opposed to spelling and writing out everything in the source code) which is possible when working a in a level above Verilog. Nice! Thanks! wbr Kusti _______________________________________________ M-Labs devel mailing list https://ssl.serverraum.org/lists/listinfo/devel
