On 30/01/2018 18:28, "Sébastien Bourdeauducq" <s...@m-labs.hk> wrote:
On Tuesday, January 30, 2018 09:10 PM, Kustaa Nyholm wrote:
> module top_level(
> output reg [11:0] out_channels [31:0],
That's not supported (do synthesizers even deal with this correctly or
try to generate a memory?). You can create 12 signals instead...
Have not tried to synthesise it (yet) but googling for this
seems that it should be supported.
But ok, I just realised that I can programmatically generate the
12 signals so that is just as well, working in a level above
*HDL is so convenient!
Thanks!
wbr Kusti
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