[PATCH RFT v2 07/15] drm/msm/a6xx: Resolve the meaning of UBWC_MODE

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>

This bit is set iff the UBWC version is 1.0. That notably does not
include QCM2290's "no UBWC".

Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 
e7c89f9c7d89798699848743843eed6a58b94bd3..6af4e70c1b936a30c1934dd49f2889be13c9780d
 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -669,10 +669,10 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
         */
        BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
        u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
+       bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg);
        bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
        u32 hbb_hi = hbb >> 2;
        u32 hbb_lo = hbb & 3;
-       u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
        u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2);
 
        gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,

-- 
2.49.0