On Tue, May 27, 2025 at 11:33:10AM +0530, Usyskin, Alexander wrote:
> > Subject: Re: [PATCH v10 05/10] mtd: intel-dg: align 64bit read and write
> >
> > On Thu, May 15, 2025 at 04:33:40PM +0300, Alexander Usyskin wrote:
> > > GSC NVM controller HW errors on quad access overlapping 1K border.
> > > Align 64bit read and write to avoid readq/writeq over 1K border.
> > >
> > > Acked-by: Miquel Raynal <miquel.ray...@bootlin.com>
> > > Signed-off-by: Alexander Usyskin <alexander.usys...@intel.com>
> > > ---
> > > drivers/mtd/devices/mtd_intel_dg.c | 35
> > ++++++++++++++++++++++++++++++
> > > 1 file changed, 35 insertions(+)
> > >
> > > diff --git a/drivers/mtd/devices/mtd_intel_dg.c
> > b/drivers/mtd/devices/mtd_intel_dg.c
> > > index eedc0974bb5b..2f32ed311ffd 100644
> > > --- a/drivers/mtd/devices/mtd_intel_dg.c
> > > +++ b/drivers/mtd/devices/mtd_intel_dg.c
> > > @@ -246,6 +246,24 @@ static ssize_t idg_write(struct intel_dg_nvm *nvm,
> > u8 region,
> > > len_s -= to_shift;
> > > }
> > >
> > > + if (!IS_ALIGNED(to, sizeof(u64)) &&
> > > + ((to ^ (to + len_s)) & GENMASK(31, 10))) {
> > > + /*
> > > + * Workaround reads/writes across 1k-aligned addresses
> > > + * (start u32 before 1k, end u32 after)
> > > + * as this fails on hardware.
> >
> > If there's a spec definition, we usually mention workarounds with
> > Wa_ID:platform so that they're easy to track. intel_workarounds.c
> > is good reference for it.
> >
> There is nothing in spec that I can find.
> Not sure that i can formalize i as workaround.
I'm a bit uninformed about the history here, but in any case I'm fine
as long as the maintainers are okay with it.
Raag
