From: Ryan Wanner <[email protected]> Write CFG(1-4) timing registers after CFG(0) clock configuration rather than before, as required by the datasheet procedure.
Signed-off-by: Ryan Wanner <[email protected]> Signed-off-by: Manikandan Muralidharan <[email protected]> --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 43 ++++++++++--------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 7932d666e9ec..9673fbce42a7 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -104,26 +104,6 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) if (ret) return; - vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay; - vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end; - vm.vsync_len = adj->crtc_vsync_end - adj->crtc_vsync_start; - vm.hfront_porch = adj->crtc_hsync_start - adj->crtc_hdisplay; - vm.hback_porch = adj->crtc_htotal - adj->crtc_hsync_end; - vm.hsync_len = adj->crtc_hsync_end - adj->crtc_hsync_start; - - regmap_write(regmap, ATMEL_HLCDC_CFG(1), - (vm.hsync_len - 1) | ((vm.vsync_len - 1) << 16)); - - regmap_write(regmap, ATMEL_HLCDC_CFG(2), - (vm.vfront_porch - 1) | ((vm.vback_porch - 1) << 16)); - - regmap_write(regmap, ATMEL_HLCDC_CFG(3), - (vm.hfront_porch - 1) | ((vm.hback_porch - 1) << 16)); - - regmap_write(regmap, ATMEL_HLCDC_CFG(4), - (adj->crtc_hdisplay - 1) | - ((adj->crtc_vdisplay - 1) << 16)); - prate = clk_get_rate(crtc->dc->hlcdc->sys_clk); mode_rate = adj->crtc_clock * 1000; if (!crtc->dc->desc->fixed_clksrc) { @@ -164,6 +144,29 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0), mask, cfg); + vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay; + vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end; + vm.vsync_len = adj->crtc_vsync_end - adj->crtc_vsync_start; + vm.hfront_porch = adj->crtc_hsync_start - adj->crtc_hdisplay; + vm.hback_porch = adj->crtc_htotal - adj->crtc_hsync_end; + vm.hsync_len = adj->crtc_hsync_end - adj->crtc_hsync_start; + + regmap_write(regmap, ATMEL_HLCDC_CFG(1), + (vm.hsync_len - 1) | + ((vm.vsync_len - 1) << 16)); + + regmap_write(regmap, ATMEL_HLCDC_CFG(2), + (vm.vfront_porch - 1) | + ((vm.vback_porch - 1) << 16)); + + regmap_write(regmap, ATMEL_HLCDC_CFG(3), + (vm.hfront_porch - 1) | + ((vm.hback_porch - 1) << 16)); + + regmap_write(regmap, ATMEL_HLCDC_CFG(4), + (adj->crtc_hdisplay - 1) | + ((adj->crtc_vdisplay - 1) << 16)); + state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state); cfg = state->output_mode << 8; -- 2.25.1
