Factor clock enable, rate calculation, and divider selection out of atmel_hlcdc_crtc_mode_set_nofb() into a new atmel_hlcdc_crtc_setup_clock() helper, preparing for the addition of LVDS and XLCDC clock bypass support.
Signed-off-by: Manikandan Muralidharan <[email protected]> --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 66 +++++++++++-------- 1 file changed, 39 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index c7e77bb2941a..6da428361c19 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -66,6 +66,42 @@ drm_crtc_to_atmel_hlcdc_crtc(struct drm_crtc *crtc) return container_of(crtc, struct atmel_hlcdc_crtc, base); } +static int atmel_hlcdc_crtc_setup_clock(struct atmel_hlcdc_crtc *crtc, + unsigned long mode_rate, + unsigned int *cfg, + unsigned int *mask) +{ + unsigned long prate; + int div, ret; + + ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + if (ret) + return ret; + + prate = clk_get_rate(crtc->dc->hlcdc->sys_clk); + if (!crtc->dc->desc->fixed_clksrc) { + prate *= 2; + *cfg |= ATMEL_HLCDC_CLKSEL; + *mask |= ATMEL_HLCDC_CLKSEL; + } + + div = DIV_ROUND_CLOSEST(prate, mode_rate); + if (div < 2) { + div = 2; + } else if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) { + /* The divider ended up too big, try a lower base rate. */ + if (!crtc->dc->desc->fixed_clksrc) { + *cfg &= ~ATMEL_HLCDC_CLKSEL; + div = DIV_ROUND_CLOSEST(prate >> 1, mode_rate); + } + if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) + div = ATMEL_HLCDC_CLKDIV_MAX; + } + + *cfg |= ATMEL_HLCDC_CLKDIV(div); + return 0; +} + static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) { struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); @@ -76,12 +112,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) struct atmel_hlcdc_crtc_state *state; struct drm_device *ddev = c->dev; struct drm_connector_list_iter iter; - unsigned long mode_rate; struct videomode vm; - unsigned long prate; unsigned int mask = ATMEL_HLCDC_CLKDIV_MASK | ATMEL_HLCDC_CLKPOL; unsigned int cfg = 0; - int div, ret; + int ret; /* get encoder from crtc */ drm_for_each_encoder(en_iter, ddev) { @@ -100,33 +134,11 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) drm_connector_list_iter_end(&iter); } - ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + ret = atmel_hlcdc_crtc_setup_clock(crtc, adj->crtc_clock * 1000, + &cfg, &mask); if (ret) return; - prate = clk_get_rate(crtc->dc->hlcdc->sys_clk); - mode_rate = adj->crtc_clock * 1000; - if (!crtc->dc->desc->fixed_clksrc) { - prate *= 2; - cfg |= ATMEL_HLCDC_CLKSEL; - mask |= ATMEL_HLCDC_CLKSEL; - } - - div = DIV_ROUND_CLOSEST(prate, mode_rate); - if (div < 2) { - div = 2; - } else if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) { - /* The divider ended up too big, try a lower base rate. */ - if (!crtc->dc->desc->fixed_clksrc) { - cfg &= ~ATMEL_HLCDC_CLKSEL; - div = DIV_ROUND_CLOSEST(prate >> 1, mode_rate); - } - if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) - div = ATMEL_HLCDC_CLKDIV_MAX; - } - - cfg |= ATMEL_HLCDC_CLKDIV(div); - if (connector && connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) cfg |= ATMEL_HLCDC_CLKPOL; -- 2.25.1
