Set the LVDS PLL rate to 7x the pixel clock. set ATMEL_XLCDC_CLKBYP for the LVDS path, leaving clock lifecycle management to the atomic callbacks and fallback to sys_clk for non-LVDS displays with proper error handling.
Signed-off-by: Manikandan Muralidharan <[email protected]> --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 45 +++++++++++++++++-- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index f837684654ea..73a8650bc9b7 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -26,6 +26,8 @@ #include "atmel_hlcdc_dc.h" +#define ATMEL_LVDS_PLL_MULT 7 + /** * struct atmel_hlcdc_crtc_state - Atmel HLCDC CRTC state structure * @@ -66,6 +68,14 @@ drm_crtc_to_atmel_hlcdc_crtc(struct drm_crtc *crtc) return container_of(crtc, struct atmel_hlcdc_crtc, base); } +static void atmel_hlcdc_crtc_disable_clock(struct atmel_hlcdc_crtc *crtc) +{ + if (crtc->dc->hlcdc->lvds_pll_clk) + clk_disable_unprepare(crtc->dc->hlcdc->lvds_pll_clk); + else + clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); +} + static int atmel_hlcdc_crtc_setup_clock(struct atmel_hlcdc_crtc *crtc, unsigned long mode_rate, unsigned int *cfg, @@ -74,6 +84,12 @@ static int atmel_hlcdc_crtc_setup_clock(struct atmel_hlcdc_crtc *crtc, unsigned long prate; int div, ret; + if (crtc->dc->hlcdc->lvds_pll_clk) { + *cfg |= ATMEL_XLCDC_CLKBYP; + *mask |= ATMEL_XLCDC_CLKBYP; + return clk_prepare_enable(crtc->dc->hlcdc->lvds_pll_clk); + } + ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); if (ret) return ret; @@ -198,7 +214,7 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) ATMEL_XLCDC_DPI : ATMEL_HLCDC_MODE_MASK), cfg); - clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + atmel_hlcdc_crtc_disable_clock(crtc); } static enum drm_mode_status @@ -254,7 +270,8 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, 10, 1000)) drm_warn(dev, "Atmel LCDC status register CLKSTS timeout\n"); - clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + atmel_hlcdc_crtc_disable_clock(crtc); + pinctrl_pm_select_sleep_state(dev->dev); pm_runtime_allow(dev->dev); @@ -267,15 +284,33 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, { struct drm_device *dev = c->dev; struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); + struct drm_display_mode *adj = &c->state->adjusted_mode; struct regmap *regmap = crtc->dc->hlcdc->regmap; unsigned int status; + int ret; pm_runtime_get_sync(dev->dev); pm_runtime_forbid(dev->dev); pinctrl_pm_select_default_state(dev->dev); - clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + + /* + * Set LVDS PLL clock rate (7x pixel clock) if available + */ + if (crtc->dc->hlcdc->lvds_pll_clk) { + ret = clk_set_rate(crtc->dc->hlcdc->lvds_pll_clk, + adj->clock * 1000 * ATMEL_LVDS_PLL_MULT); + if (ret) { + drm_err(dev, "Failed to set LVDS PLL clk rate: %d\n", ret); + goto err_clk; + } + ret = clk_prepare_enable(crtc->dc->hlcdc->lvds_pll_clk); + } else { + ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + } + if (ret) + goto err_clk; regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK); if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, @@ -310,7 +345,11 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, } pm_runtime_put_sync(dev->dev); + return; +err_clk: + pm_runtime_allow(dev->dev); + pm_runtime_put_sync(dev->dev); } #define ATMEL_HLCDC_RGB444_OUTPUT BIT(0) -- 2.25.1
