On Thu, 7 Mar 2002, José Fonseca wrote:
> Ok. I'm gonna look into this tomorrow. Both the r128 and radeon drivers
> have PCI support, so it shouldn'be difficult to bring the PCI support to
> the same state as the AGP (i.e., just initialize it).
The quickest fix to make things easier for testers would probably be to
just disable the AGP/PCI init in the DRM for now, since it's not really
necessary yet. If we get PCI support added or start working on DMA, then
we could enable it again to test it out.
> BTW, I just commited initial support for the tex coord premultiplication
> in the mach64-0-0-3-branch. This doesn't help with the lockups in multiarb
> though.
I checked it out and it looks like the texcoords would get multiplied by
the rhw _and_ multiplied by w. Also, the utah-glx code and the previous
branch multiplied the w coord by the fourth texture coord, if there is
one. I haven't tested this yet, but I'll inline my diff here since it's
small. I'm going to try to find out where multiarb is choking, since it
shouldn't lock the card even if the texcoords are wrong.
Index: mach64_vbtmp.h
===================================================================
RCS file: /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/mach64/Attic/mach64_vbtmp.h,v
retrieving revision 1.1.2.1
diff -u -r1.1.2.1 mach64_vbtmp.h
--- mach64_vbtmp.h 7 Mar 2002 01:28:53 -0000 1.1.2.1
+++ mach64_vbtmp.h 7 Mar 2002 16:39:00 -0000
@@ -258,6 +258,10 @@
if (DO_TEX0) {
v->v.u0 = tc0[0][0];
v->v.v0 = tc0[0][1];
+#ifdef MACH64_PREMULT_TEXCOORDS
+ v->v.u0 *= v->v.w;
+ v->v.v0 *= v->v.w;
+#endif
if (DO_PTEX) {
if (HAVE_PTEX_VERTICES) {
if (tc0_size == 4)
@@ -266,16 +270,16 @@
v->pv.q0 = 1.0;
}
else if (tc0_size == 4) {
+#ifdef MACH64_PREMULT_TEXCOORDS
+ v->v.w *= tc0[0][3];
+#else
float rhw = 1.0 / tc0[0][3];
v->v.w *= tc0[0][3];
v->v.u0 *= rhw;
v->v.v0 *= rhw;
+#endif
}
}
-#ifdef MACH64_PREMULT_TEXCOORDS
- v->v.u0 *= v->v.w;
- v->v.v0 *= v->v.w;
-#endif
tc0 = (GLfloat (*)[4])((GLubyte *)tc0 + tc0_stride);
}
if (DO_TEX1) {
@@ -364,6 +368,10 @@
if (DO_TEX0) {
v->v.u0 = tc0[i][0];
v->v.v0 = tc0[i][1];
+#ifdef MACH64_PREMULT_TEXCOORDS
+ v->v.u0 *= v->v.w;
+ v->v.v0 *= v->v.w;
+#endif
if (DO_PTEX) {
if (HAVE_PTEX_VERTICES) {
if (tc0_size == 4)
@@ -374,16 +382,16 @@
v->pv.q1 = 0; /* radeon */
}
else if (tc0_size == 4) {
+#ifdef MACH64_PREMULT_TEXCOORDS
+ v->v.w *= tc0[i][3];
+#else
float rhw = 1.0 / tc0[i][3];
v->v.w *= tc0[i][3];
v->v.u0 *= rhw;
v->v.v0 *= rhw;
+#endif
}
}
-#ifdef MACH64_PREMULT_TEXCOORDS
- v->v.u0 *= v->v.w;
- v->v.v0 *= v->v.w;
-#endif
}
if (DO_TEX1) {
if (DO_PTEX) {
--
Leif Delgass
http://www.retinalburn.net
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