On 14/03/2016 10:51, Ni, Ruiyu wrote: > > The layout of CpuSaveState is different from what is described in > Intel IA32 manual. Seems QEMU specific. > The CpuSaveState pointer is correct. > I dumped the CpuSaveState content. The SMMBase and SMMRevId > is correct. But EAX is incorrect.
I have already explained many times that the different CpuSaveState layout is because Intel refuses to document in the SDM the _actual_ contents of the SMM save state area, most notably the placement of the descriptor cache registers. Since AMD's documentation is crystal clear (except that it's partly split between the programmer's manual and the BIOS/kernel writer manual), we went with the AMD format. Paolo _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
