Paolo, Laszlo, As I mentioned in previous mail, the EAX I got from CpuSaveState is different from what I set before entering SMM. Because the failure was seen in a QEMU launched in Windows using the following command: qemu-system-x86_64.exe \ -machine q35,smm=on,accel=tcg \ -smp 1 \ -drive if=pflash,format=raw,unit=0,file=OVMF_CODE.fd,readonly=on \ -drive if=pflash,format=raw,unit=1,file=OVMF_VARS.fd \ --serial COM5
I guess you should use Linux to run QEMU. So I switched to Ubuntu 14.04. 1. Upgraded the kernel to 4.4.1. 2. Download the QEMU 2.5 source and make 3. run the following command: qemu-system-x86_64 \ -display none \ -machine q35,smm=on,accel=kvm \ -global driver=cfi.pflash01,property=secure,value=on \ -drive if=pflash,format=raw,unit=0,file=Build/Ovmf3264/DEBUG_GCC49/FV/OVMF_CODE.fd,readonly=on \ -drive if=pflash,format=raw,unit=1,file=Build/Ovmf3264/DEBUG_GCC49/FV/OVMF_VARS.fd \ --serial file:ovmf.log But the system hung. The very last several lines of ovmf.log are: Loading SMM driver at 0x00007FAE000 EntryPoint=0x00007FAE28F PiSmmCpuDxeSmm.efi SMRR Base: 0x7800000, SMRR Size: 0x800000 PcdCpuSmmCodeAccessCheckEnable = 1 SMRAM TileSize = 0x00002000 (0x00001000, 0x00001000) SMRAM SaveState Buffer (0x07FA6000, 0x00008000) CPU[000] APIC ID=0000 SMBASE=07F9E000 SaveState=07FADC00 Size=00000400 Is there any mistake I made? Regards, Ray >-----Original Message----- >From: Paolo Bonzini [mailto:[email protected]] On Behalf Of Paolo Bonzini >Sent: Monday, March 14, 2016 9:52 PM >To: Ni, Ruiyu <[email protected]>; Laszlo Ersek <[email protected]>; Justen, >Jordan L <[email protected]> >Cc: [email protected] <[email protected]> >Subject: Re: [edk2] Software SMI STS bit is not set when writing port B2 in >QEMU Q35 > > > >On 14/03/2016 10:51, Ni, Ruiyu wrote: >> >> The layout of CpuSaveState is different from what is described in >> Intel IA32 manual. Seems QEMU specific. >> The CpuSaveState pointer is correct. >> I dumped the CpuSaveState content. The SMMBase and SMMRevId >> is correct. But EAX is incorrect. > >I have already explained many times that the different CpuSaveState >layout is because Intel refuses to document in the SDM the _actual_ >contents of the SMM save state area, most notably the placement of the >descriptor cache registers. Since AMD's documentation is crystal clear >(except that it's partly split between the programmer's manual and the >BIOS/kernel writer manual), we went with the AMD format. > >Paolo _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
