On 07/05/16 12:54, Laszlo Ersek wrote:
> On 07/04/16 09:38, Ni, Ruiyu wrote:
>> Adding Kinney.
>>
>> Laszlo,
>> Your patch assumes all PCIE slot are hot plug capable.
>
> Yes, it does assume that.
>
>> But why PCIE spec 3.0 chapter 7.8.9 Slot Capabilities Register (Offset 14h)
>> contains a BIT called Hot-Plug Capable?
>> Does your patch also need to check the Hot-Plug Capable bit as well?
>
> I don't know :) I tried to follow the logic that I found in SeaBIOS and
> in UefiShellDebug1CommandsLib.
>
> I think this is a valid question, of course. I'd just like to forward it
> to Marcel and Alex :) It is perfectly possible, as far as I understand,
> that QEMU's virtual hardware guarantees a "shortcut" that is not a given
> with physical hardware. So if the check must be restricted a bit, I'm
> glad to do it.
I checked the QEMU implementation in:
- hw/pci-bridge/xio3130_downstream.c (downstream port)
- hw/pci-bridge/ioh3420.c (root port)
They both call pcie_cap_slot_init().
The pcie_cap_slot_init() function [hw/pci/pcie.c] sets the "Hot-Plug Capable"
bit (= bit 6) in the Slot Capabilities Register (Offset 14h):
uint32_t pos = dev->exp.exp_cap;
...
pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
(slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
PCI_EXP_SLTCAP_EIP |
PCI_EXP_SLTCAP_HPS |
PCI_EXP_SLTCAP_HPC |
PCI_EXP_SLTCAP_PIP |
PCI_EXP_SLTCAP_AIP |
PCI_EXP_SLTCAP_ABP);
where the relevant macros are [include/standard-headers/linux/pci_regs.h]:
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
...
#define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
Also, from the PCIe spec ("7.8. PCI Express Capability Structure"):
[...] The Slot Capabilities register is required if the Slot Implemented
bit is
Set (see Section 7.8.2). [...]
so it shouldn't be hard to implement your suggestion for v2 of this patch; I'll
do it.
Thanks!
Laszlo
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