Hi Phil,
There is no inherent reason why the MDS could not be that low in
direct sampling SDRs. It is mainly a matter of design
decision/implementation.
This may be a stupid (or at least ignorant) question, but if the dynamic
range of the ADC itself is defined by the number of bits it resolves and
a maximum voltage must never (should never) be exceeded, wouldn't
improving MDS by 10 to 15db create major problems with the high end of
the scale? I would tend to think that analog solutions could be more
forgiving or that the K3 path which provides an AGC to protect the ADC
might be (at present) a "better" way to go.
Or are you suggesting using much faster ADCs so that you have a higher
level of over sampling, allowing more process gain during decimation?
vy 73 de toby
_______________________________________________
Elecraft mailing list
Post to: [email protected]
You must be a subscriber to post to the list.
Subscriber Info (Addr. Change, sub, unsub etc.):
http://mailman.qth.net/mailman/listinfo/elecraft
Help: http://mailman.qth.net/subscribers.htm
Elecraft web page: http://www.elecraft.com
