Minimal NDA probably exists already - RISCV code, that's as close as you could get without starting to sign NDAs, unless you target an ancient process, even then it won't necessarily be prodicible.
I think getting a handful of people together and targeting an ancient node would be fun, but I'd aim for something even simpler than RISCV. On May 16, 2017 1:41 AM, "Maurício Carvalho" <[email protected]> wrote: > Thank you Travis and Patryk! > > I have a few remarks though: > > 1) The idea is to set up open source hardware and tools for ASIC design > (Digital and Analog) to reduce as many NDAs as I can. The idea behind this > to make ASIC design freely available to whoever wants to develop their own > design. Last year I was an ASIC design instructor linked to an University > in the south of Brazil. I taught DFT and test to engineers, but focusing on > "piloting" EDA tools and the ASIC design flow. I was also involved in some > designs linked to research. The course is fabulous and it teaches ASIC > design thoroughly that one would not learn in regular university courses > unless they have worked in the industry on a real design. However, before > attending this 2-year hands-on specialized course, our students needed to > sign EDA/CAD NDA contracts committing to not use it on any commercial > activity, as well as to keep every material and scripts they produced > secret to themselves or to whoever is involved. In addition, you'd often > see many students with entrepreneur skills keen on developing their own > ASIC projects (after studying viability to market and design feasibility) > but they'd need to pay EDA licenses which are very costly. On the > fabrication part, there are several multiuser projects out there that they > can use, specially if this open source platform is finely tuned for a > target Foundry. > > 2) I have designed a few CPU cores for academic research as well as worked > on a few commercial CPU cores. I have also used the openrisc1200 and I > admire it, but I would really like to develop my own CPU with a free ISA > based on the RISCV. (This part is personal). However, any case study CPU > would be fine, in order to set up the open source ASIC platform (kind of > like Fedora had once, namely FEL) but I would also add free to use scripts, > IDEs and everything needed so that one can actually produce a professional > sign-off and send it to the target Foundry. > > 3) I have no intention to manufacture it in a garage, but could be a > future challenge, probably with the help of others (if that's even > possible). > > > Please feel free to add as many problems I may find and probable solutions! > > Kind regards, > Mauricio De Carvalho > > > On Mon, May 15, 2017 at 10:39 PM, Patryk S <[email protected]> wrote: > >> https://opencores.org >> https://en.wikipedia.org/wiki/OpenCores >> >> 2017-05-15 19:25 GMT+02:00 Travis Ayres <[email protected]>: >> >>> The NDAs for the foundaries will stop you cold as soon as you go below >>> about 180nm. >>> >>> An option would be to use laser direct writing and expose and dope the >>> wafers yourself. You could theoretically do this in a clean room you setup >>> in a garage, but you'd still probably need 40k of equipment and material, >>> at the very low end. Disposal of toxic chemicals in an appropriate way is >>> another hurdle. All of this, and you might be able to get an ancient >>> process out the door. But it would be fun... >>> >>> >>> >>> On May 15, 2017 6:31 AM, "Justin Spencer" <[email protected]> >>> wrote: >>> >>>> Dear Mr. Carvalho, >>>> >>>> Good day. I would also like to help with this endeavor in any way >>>> possible. >>>> Please contact me if you're interested in collaborating. >>>> >>>> Thank you. >>>> >>>> Regards, >>>> Justin >>>> >>>> On Friday, 24 March 2017 00:33:22 UTC+8, Maurício Carvalho wrote: >>>>> >>>>> Hi everyone, >>>>> >>>>> I would like to develop a full open source RISCV-based System-On-Chip >>>>> making use of free VLSI tools and PDKs (possibly making everything freely >>>>> available). I have been playing with electric vlsi for some years but I >>>>> never did anything serious with it besides playing with small designs and >>>>> doing simple tests. On industry standard tools, however, I have been doing >>>>> a couple of serious professional works and I have a reasonable >>>>> understanding of the digital and analog flow. >>>>> >>>>> I have a few questions regarding electric and my goal: >>>>> >>>>> 1) I'd like to know if electric could work well with distributed >>>>> computing for physical synthesis and other computing intense work. For >>>>> example, If I have a powerful workstation including several CPUs and such, >>>>> would it correctly make use of the system's resources? >>>>> >>>>> 2) I have found some open source PDKs, but I could never find an >>>>> answer whether they can produce a reliable layout and the relative foundry >>>>> where it can be actually manufactured. I presume someone has already >>>>> manufactured a design, possibly with MOSIS PDKs, using Electric? Any other >>>>> suggestions are welcome. I have found a .18 library, but I would like to >>>>> use sub-micron technologies 90nm, 65nm and 45nm. I guess listing as many >>>>> open source PDKs related to a specific Foundry as I can would also help. >>>>> >>>>> 3) What about automated DFT in electric? Sure we can manually add some >>>>> blocks at the RTL, but scan chains can be quite difficult to implement >>>>> without useful information from the synthesized circuit. What about ATPGs? >>>>> Are there any possibility to integrate these tools on electric? Or, are >>>>> there any open source Test Tools? I've asked for the Lifting fault >>>>> simulation tool but never got an answer back from the developers. >>>>> >>>>> 4) Is there an SDC equivalent for Electric during logic and physical >>>>> synthesis? >>>>> >>>>> 5) Does anyone know where I can find an open source memory cell? Or a >>>>> very cheap one which would include models for logic and electrical >>>>> simulations? >>>>> >>>>> I'm sure there are many other questions I'd like to add to this post, >>>>> but it is best to keep it short for now. >>>>> >>>>> Hope someone can help! >>>>> >>>>> Regards, >>>>> Mauricio De Carvalho >>>>> >>>>> >>>> -- >>>> You received this message because you are subscribed to the Google >>>> Groups "Electric VLSI Editor" group. >>>> To unsubscribe from this group and stop receiving emails from it, send >>>> an email to [email protected]. >>>> For more options, visit https://groups.google.com/d/optout. >>>> >>> -- >>> You received this message because you are subscribed to the Google >>> Groups "Electric VLSI Editor" group. >>> To unsubscribe from this group and stop receiving emails from it, send >>> an email to [email protected]. >>> For more options, visit https://groups.google.com/d/optout. >>> >> >> -- >> You received this message because you are subscribed to a topic in the >> Google Groups "Electric VLSI Editor" group. >> To unsubscribe from this topic, visit https://groups.google.com/d/to >> pic/electricvlsi/VrETJDlTc8Q/unsubscribe. >> To unsubscribe from this group and all its topics, send an email to >> [email protected]. >> For more options, visit https://groups.google.com/d/optout. >> > > -- > You received this message because you are subscribed to the Google Groups > "Electric VLSI Editor" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > For more options, visit https://groups.google.com/d/optout. > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. 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