Hello Mauricio! I've seen a webinar[1] where they show how is implemented a picorv[2] plus other peripherals to get a SoC in 180nm using the efabless.com website. There you use electric for schematic capture, ngspice for the analog and mixed signal and qflow for rhe digital. You can login in that site and get all tools already configured with the PDKs and import some analog IP blocks from an available library. Regards, Leandro
[1]:https://m.youtube.com/watch?v=TrTp572FgFo [2]: https://github.com/cliffordwolf/picorv32 El jueves, 23 de marzo de 2017, Maurício Carvalho <[email protected]> escribió: > Hi everyone, > > I would like to develop a full open source RISCV-based System-On-Chip making use of free VLSI tools and PDKs (possibly making everything freely available). I have been playing with electric vlsi for some years but I never did anything serious with it besides playing with small designs and doing simple tests. On industry standard tools, however, I have been doing a couple of serious professional works and I have a reasonable understanding of the digital and analog flow. > > I have a few questions regarding electric and my goal: > > 1) I'd like to know if electric could work well with distributed computing for physical synthesis and other computing intense work. For example, If I have a powerful workstation including several CPUs and such, would it correctly make use of the system's resources? > > 2) I have found some open source PDKs, but I could never find an answer whether they can produce a reliable layout and the relative foundry where it can be actually manufactured. I presume someone has already manufactured a design, possibly with MOSIS PDKs, using Electric? Any other suggestions are welcome. I have found a .18 library, but I would like to use sub-micron technologies 90nm, 65nm and 45nm. I guess listing as many open source PDKs related to a specific Foundry as I can would also help. > > 3) What about automated DFT in electric? Sure we can manually add some blocks at the RTL, but scan chains can be quite difficult to implement without useful information from the synthesized circuit. What about ATPGs? Are there any possibility to integrate these tools on electric? Or, are there any open source Test Tools? I've asked for the Lifting fault simulation tool but never got an answer back from the developers. > > 4) Is there an SDC equivalent for Electric during logic and physical synthesis? > > 5) Does anyone know where I can find an open source memory cell? Or a very cheap one which would include models for logic and electrical simulations? > > I'm sure there are many other questions I'd like to add to this post, but it is best to keep it short for now. > > Hope someone can help! > > Regards, > Mauricio De Carvalho > > > -- > You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. > To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. > For more options, visit https://groups.google.com/d/optout. > -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
