Nice as a Joke, but I already use a 10 MIPS CPU to do much more
interrupts than the 2GHz PC processors can handle...

Okay everybody, why do we use the crappy PC processors - because of
price - and we are lacking the PowerPC compilers directives like where
to store what... you can direct PPC compiler to store context saving
in any CPU cache you want, why we could NOT do it in PC processor?
Today the Cache levels are huge! We also might wan to use the internal
CPU timer - if it can make interrupts in low latency. And as someone
here posted info about some board (could not be bought at that time)
that integrated only a lame Xilinix gate array tha produced up to 4.7
milion quadrature output changes on many outputs and even had
quadrature encoder inputs for feedback because it also incorporated a
G-code interpreter in itself!

So what do we want is to make things smaller to fit and switch faster
and if possible ask processor to keep certain parts in cache, or
simply force it to do it by various tricks.

It is easy to to a gaziolion switches between something you have in
cache, it is not easy if you have it outside the CPU.

On 11/5/07, Jon Elson <[EMAIL PROTECTED]> wrote:
> Mario. wrote:
> > Ehm, if it would be possible with any processor to reach a 500 kHz
> > interrupt rate, I would be in heaven suddenly.
> 500 KHz?  I think you'll need to wait for the 1 nm feature size
> version of the Pentium 9000, with 250 billion transistors on the
> chip, and a clock of 250 GHz.  500 Khz interrupts would leave
> only 2 us between interrupts.  With the context to save going up
> with every revision, we probably won't ever get there in an X86
> architecture.  Some of the hot DSP processors can do this today,
> they have VERY LITTLE CPU context to store.  Still, you can't do
> a whole lot in 2 us.  I guess you could actually toggle a
> parallel port bit that fast, too, if the CPU could handle it.
>
> Jon
>
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