Thanks a lot for your inputs.

All responses to my second question are only concerned with the inductance due 
to “long” distance between chip and decap. Nobody seems to agree imposing 
another constrain to the distance. My question was

“Do we really have to limit the distance letting the charge have enough time to 
move from the cap to the chip during the rise time interval? I doubt it.” 
 
But I really read an article implying this extra concern.


George, you wrote:
> This is true if you have only DC current.  For AC, you may have water in the 
> pipe but 
> no water out of the faucet if the faucet is switching out of phase from the 
> water in 
> the pipe.

Thank you for reminding me of Frequency Domain analysis. Yes, I should have 
described and analyzed a transient problem (charge travel during Tr) in both TD 
and FD, and then correlate the results.  Let me have a try this time: 

It is generally acknowledged that decaps and plane cap are complementary 
(supposing a 10 mil or less spacing between pwr and gnd planes). Decaps cover 
low end of frequency range, while the plane cap takes care of high frequencies. 
Thus the interplane cap would play more and more important role in high-speed 
PCB design, as the speed gets faster and faster. On the other hand, nobody 
objects closer distances from decaps to the chip, if possible. ..... When a 
chip drains necessary charges from pwr/gnd planes during Tr, decaps would 
supply charges to pwr and gnd planes on lower frequencies, while interplane cap 
can respond itself on higher frequencies.

Best Regards,
Barry Ma
[email protected]



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