Barry Ma wrote:
>
> Hi,
>
> As the speed of digital signals gets faster and faster, people begin being
> concerned
> with the distance for electric charge to move on power and ground planes of
> multilayer
> PCB during the signal rise time from a decoupling capacitor (cap) to a chip
> it serves.
> I would like to raise two questions.
>
> (1) The charge is moving in a metalic plane, not inside the dielectric
> between pwr and
> gnd planes. Please let me know why you have to use the propagation velocity
> in the
> dielectric, instead of that in the metal.
Simple. The power/ground plane construction is
a 2-dimensional transmission line. Just as you
determine the velocity of propagation in a
1-dimensional transmission line, the dielectric
is part of the equation for the capacitive
component. And so it follows with the planar
construction.
> (2) The second question is regarding distance between the cap and the chip.
> Do we
> really have to limit the distance letting the charge have enough time to move
> from
> the cap to the chip during the rise time interval? I doubt it.
Depends. Distance can mean inductance.
Since, v(t) = L di/dt and with L in nano-henries (10^-9)
and suppose dt in pico-seconds (10^-12), we're already
up in the 10^3 range ... - Doug McKean
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