On Wed, 6 Sep 2006 12:20:12 -0400
"Sterner, David [S&FS]" <[email protected]>
wrote:
...snip...
> requires an impractically large sample. Many IC ESD
> failure mechanisms
> are catastrophic and therefore not repeatable, further
> complicating
> statistical treatment.
...and worse, some mechanisms of "failure" are insidious.
Extremely shortening chip lifetime. Those don't show up
during the test, but the chip is doomed and fails within a
month, or two.
- Robert -
-
This message is from the IEEE Product Safety Engineering Society
emc-pstc discussion list. Website: http://www.ieee-pses.org/
To post a message to the list, send your e-mail to [email protected]
Instructions: http://listserv.ieee.org/request/user-guide.html
List rules: http://www.ieee-pses.org/listrules.html
For help, send mail to the list administrators:
Scott Douglas [email protected]
Mike Cantwell [email protected]
For policy questions, send mail to:
Jim Bacher: [email protected]
David Heald: [email protected]
All emc-pstc postings are archived and searchable on the web at:
http://www.ieeecommunities.org/emc-pstc
______________________________________________________________________
This email has been scanned by the MessageLabs Email Security System.
For more information please visit http://www.messagelabs.com/email
______________________________________________________________________
