Hi Sylvia, The best way to approach this is using the same DVT ( Design Verification Test) profile that was used to qualify the original product/memory. It may not be necessary to run it through the full suite of DVT tests but that would be a good place to start until you build up an acceptable confidence level. Once you have a high confidence level ( low failure rate) you may choose to run a subset of your DVT profile to qualify new vendor chips. Since I do not know your product or HW I cannot suggest specific DVT tests but hopefully your company has some documented process to ensure system performance and reliability prior to releasing a product to market. Additionally, you may want to start performing a reliability demonstration test ( RDT) on some specified number of units to ensure these units can run without error over a specified time line at a slightly elevated temperature but still within the operating temperature range of the product. These units should be running your diagnostic SW program or running at maximum capacity during the RDT. The important thing you want to get out of this is to find a consistent reliable way to screen your product when making changes to the memory chip and to ensure all anomalies are caught internally and not at your customer site. Best, Jeff Collins Compliance & Reliability www.six9sreliable.com <http://www.six9sreliable.com/>
--- On Wed, 6/10/09, Sylvia Toma <[email protected]> wrote: From: Sylvia Toma <[email protected]> Subject: end-product testing To: [email protected], [email protected] Date: Wednesday, June 10, 2009, 11:41 AM Dear experts, Could you shed some light as to what type of tests or checking one might do in an end product when qualifying alternate memory chips (SDRAM, DRAM, etc.)? Memory vendors generally do their own functional testing before product is shipped. Functional tests usually include VCC speed verification, VCC margin, VCC bump, Dynamic and static research and a full range of array exercising algorithms. As much as this is being done, we still see occasional failures in end-product due to manufacturing defect of the chip or process breakdown at the chip manufacturing location. I'm looking forward to your guidance. Regards Sylvia - This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. To post a message to the list, send your e-mail to <[email protected] <http://us.mc301.mai .yahoo.com/mc/[email protected]> > All emc-pstc postings are archived and searchable on the web at http://www.ieeecommunities.org/emc-pstc Graphics (in well-used formats), large files, etc. can be posted to that URL. Website: http://www.ieee-pses.org/ Instructions: http://listserv.ieee.org/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas <[email protected] <http: /us.mc301.mail.yahoo.com/mc/[email protected]> > Mike Cantwell <[email protected] <http //us.mc301.mail.yahoo.com/mc/[email protected]> > For policy questions, send mail to: Jim Bacher <[email protected] <http://u .mc301.mail.yahoo.com/mc/[email protected]> > David Heald <[email protected] <http://u .mc301.mail.yahoo.com/mc/[email protected]> > - This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. To post a message to the list, send your e-mail to <[email protected]> All emc-pstc postings are archived and searchable on the web at http://www.ieeecommunities.org/emc-pstc Graphics (in well-used formats), large files, etc. can be posted to that URL. Website: http://www.ieee-pses.org/ Instructions: http://listserv.ieee.org/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas <[email protected]> Mike Cantwell <[email protected]> For policy questions, send mail to: Jim Bacher <[email protected]> David Heald <[email protected]>
