Dear experts,
Could you shed some light as to what type of tests or checking one might do in an end product when qualifying alternate memory chips (SDRAM, DRAM, etc.)? Memory vendors generally do their own functional testing before product is shipped. Functional tests usually include VCC speed verification, VCC margin, VCC bump, Dynamic and static research and a full range of array exercising algorithms. As much as this is being done, we still see occasional failures in end-product due to manufacturing defect of the chip or process breakdown at the chip manufacturing location. I'm looking forward to your guidance. Regards Sylvia - This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. To post a message to the list, send your e-mail to <[email protected]> All emc-pstc postings are archived and searchable on the web at http://www.ieeecommunities.org/emc-pstc Graphics (in well-used formats), large files, etc. can be posted to that URL. Website: http://www.ieee-pses.org/ Instructions: http://listserv.ieee.org/request/user-guide.html List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas <[email protected]> Mike Cantwell <[email protected]> For policy questions, send mail to: Jim Bacher <[email protected]> David Heald <[email protected]>
